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부품번호 W3HG264M72EER-AD7 기능
기능 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED
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W3HG264M72EER-AD7 데이터시트, 핀배열, 회로
White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4UA.cDoVmANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL,
VLP Mini-DIMM
FEATURES
244-pin, very low profile dual in-line memory
module (VLP Mini-DIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300*, and PC2-6400*
Supports ECC error detection and correction
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL)
Posted CAS# additive latency (AL)
On-die termination (ODT)
Programmable burst lenghts: 4 or 8
Serial Presence Detect (SPD) with EEPROM
Auto and Self Refresh Capability (64ms: 8,192
cycle refresh)
Gold (Au) edge contacts
RoHS compliant
Dual Rank
Package option
• 244 Pin Mini-DIMM
• PCB – 18.29mm (0.72")
DESCRIPTION
The W3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity option
Clock Speed
CL-tRCD-tRP
* Contact factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
December 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3HG264M72EER-AD7 pdf, 반도체, 판매, 대치품
White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4U.AcDomVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Supply voltage
I/O Supply voltage
VCCL Supply voltage
I/O Reference voltage
I/O Termination voltage
Symbol
VCC
VCCQ
VCCL
VREF
VTT
Min
1 .7
1 .7
1 .7
0.49 x VCCQ
VREF-0.04
Typical
1 .8
1 .8
1 .8
0.50 x VCCQ
VREF
Max
1 .9
1 .9
1 .9
0.51 x VCCQ
VREF + 0.04
Unit
V
V
V
V
V
Notes
1
4
4
2
3
Notes:
1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC.
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not excedd ±1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM DC RATINGS
Symbol Parameter
MIN MAX U nit
VCC Voltage on VCC pin relative to VSS
-1.0 2.3
V
VCCQ
Voltage on VCCQ pin relative to VSS
-0.5 2.3
V
VCCL Voltage on VCCL pin relative to VSS
-0.5 2.3
V
VIN, VOUT Voltage on any pin relative to VSS
-0.5 2.3
V
TSTG Storage temperature
-55 100 °C
TCASE
Device operating temperature
0 85 °C
TOPR Operating temperature (ambient)
0 55 °C
Command/Address,
RAS#, CAS#, WE#,
-5
5
µA
IL
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
-5 5 µA
DM -5 5 µA
IOZ
Output leakage current;
0V<VOUT<VCCQ; DQs and ODT are disable
DQ, DQS, DQS#
-10
10
µA
IVREF VREF leakage current; VREF = Valid VREF level
-18 18 µA
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK0, CK0#)
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
Symbol
Min
Max
Unit
CIN1 pF
CIN2 pF
CIN3 pF
CIN4 pF
CIN5 pF
COUT1
pF
December 2005
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










W3HG264M72EER-AD7 전자부품, 판매, 대치품
White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4U.AcDomVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806 667 534 403
PARAMETER
Clock cycle time
CK high-level width
CK low-level width
Half clock period
CL = 6
CL = 5
CL = 4
CL = 3
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
SYMBOL
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
tCL
tHP
MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tAC TBD
tHZ
TBD
MAX MIN MAX MIN MAX MIN MAX UNIT Notes
TBD ps 16, 24
TBD 3,000 8,000
ps 16, 24
TBD 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24
TBD 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24
TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18
TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18
MIN MIN MIN
TBD (tCH, (tCH, (tCH,
tCL) tCL) tCL)
ps 19
TBD -450 +450 -500 +500 -600 +600 ps
tAC tAC tAC ps 8, 9
TBD
(MAX)
MAX
MAX
Data-out low-impedance window from CK/CK# tLZ
tAC tAC tAC tAC tAC tAC ps 8, 10
TBD TBD (MIN) (MAX) (MIN) (MAX) (MIN) (MAX)
DQ and DM input setup time relative to DQS
tDSa
100 100 100
TBD TBD
ps 7, 15,
21
DQ and DM input hold time relative to DQS
tDHa
175 225 275
TBD TBD
ps 7, 15,
21
DQ and DM input setup time relative to DQS
tDSb
100 100 150 tCK 7, 15,
TBD TBD
21
DQ and DM input hold time relative to DQS
tQHb
175 225 275
TBD TBD
ps 7, 15,
21
DQ…DQS hold, DQS to first DQ to go
tDIPW
0.35 0.35 0.35
nonvalid, per access relative to DQS
TBD TBD
ps
Data hold skew factor
tQHS
TBD TBD
340
400
450
DQ–DQS hold, DQS to first DQ to go nonvalid, tQH
tHP- tHP- tHP-
per access
TBD TBD tQHS
tQHS
tQHS
15, 17
Data valid output window (DVW)
tDVW
tQH-
TBD TBD tDQSQ
tQH-
tDQSQ
tQH-
tDQSQ
15, 17
DQS input high pulse width
tDQSH
TBD TBD 0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
TBD TBD 0.35
0.35
0.35
tCK
DQS output access time from CK/CK#
tDQSCK TBD TBD -400 +400 -450 +450 -500 +500 ps
DQS falling edge to CK rising– setup time
tDSS
0.2 0.2 0.2 tCK
TBD TBD
DQS falling edge from CK rising – hold time
tDSH
0.2 0.2 0.2 tCK
TBD TBD
DQS–DQ skew, DQS to last DQ valid, per
tDQSQ
240 300 350 ps 15, 17
group, per access
TBD TBD
DQS read preamble
tRPRE TBD TBD 0.9 1.1 0.9 1.1 0.9 1.1 tCK 35
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
December 2005
Rev. 0
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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1GB - 2x64Mx72 DDR2 SDRAM REGISTERED

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