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기능 Virtex Field Programmable Gate Array
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XCV50 데이터시트, 핀배열, 회로
0
Virtex™ 2.5 VR www.DataSheet4U.com
Field Programmable Gate Arrays
DS003-1 (v2.5 ) April 2, 2001
0 0 Product Specification
Features
• Fast, high-density Field-Programmable Gate Arrays
- Densities from 50k to 1M system gates
- System performance up to 200 MHz
- 66-MHz PCI Compliant
- Hot-swappable for Compact PCI
• Multi-standard SelectIO™ interfaces
- 16 high-performance interface standards
- Connects directly to ZBTRAM devices
• Built-in clock-management circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock control
- Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
• Hierarchical memory system
- LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Configurable synchronous dual-ported 4k-bit
RAMs
- Fast interfaces to external high-performance RAMs
• Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by FPGA Foundation™ and Alliance
Development Systems
- Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstation platforms
• SRAM-based in-system configuration
- Unlimited re-programmability
- Four programming modes
• 0.22 µm 5-layer metal process
• 100% factory tested
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 µm CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
Table 1: Virtex Field-Programmable Gate Array Family Members
Device
Maximum
System Gates CLB Array Logic Cells Available I/O
XCV50
57,906
16x24
1,728
180
XCV100
108,904
20x30
2,700
180
XCV150
164,674
24x36
3,888
260
XCV200
236,666
28x42
5,292
284
XCV300
322,970
32x48
6,912
316
XCV400
468,252
40x60
10,800
404
XCV600
661,111
48x72
15,552
512
XCV800
888,439
56x84
21,168
512
XCV1000
1,124,022
64x96
27,648
512
Block RAM
Bits
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
Maximum
SelectRAM+™ Bits
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1




XCV50 pdf, 반도체, 판매, 대치품
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Revision History
www.DataSheet4U.com
Date
11/98
01/99
02/99
05/99
05/99
07/99
09/99
01/00
01/00
03/00
05/00
05/00
09/00
10/00
04/01
Version
1.0
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
Revision
Initial Xilinx release.
Updated package drawings and specs.
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, 0hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to
TOPHASE.
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
Modified Pins not listed ...statement. Speed grade update to Final status.
Modified Table 18.
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
Corrected BG256 Pin Function Diagram.
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See Virtex Data Sheet section.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Module 1 of 4
4
www.xilinx.com
1-800-255-7778
DS003-1 (v2.5 ) April 2, 2001
Product Specification

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XCV50 전자부품, 판매, 대치품
R Virtex2.5 V Field Programmable Gate Arrays
Input Path
A buffer In the Virtex IOB input path routes the input signal
either directly to internal logic or through an optional input
flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can used in close proximity
to each other. See I/O Banking, page 3.
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 k100 k.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
ing, page 3.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate VREF voltage must
be provided if the signalling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages externally and con-
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from sepwarwawtin.DgateaaShcehete4dUg.ceomof the
FPGA into two banks, as shown in Figure 3. Each bank has
multiple VCCO pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Bank 0
Bank 1
GCLK3 GCLK2
Virtex
Device
GCLK1 GCLK0
Bank 5
Bank 4
X8778_b
Figure 3: Virtex I/O Banks
Within a bank, output standards can be mixed only if they
use the same VCCO. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on VCCO.
Table 2: Compatible Output Standards
VCCO
3.3 V
Compatible Standards
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+
2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The VREF pins within a bank are interconnected internally
and consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require VREF can be mixed with
those that do not. However, only one VREF voltage can be
used within a bank. Input buffers that use VREF are not 5 V
tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
The VCCO and VREF pins for each bank appear in the device
Pinout tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
3

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