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W78M32V-XBX 데이터시트 PDF




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부품번호 W78M32V-XBX 기능
기능 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package
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W78M32V-XBX 데이터시트, 핀배열, 회로
White Electronic Designs
W78M32V-XBX
www.DataSheet4U.com
8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write
Operation Multi-Chip Package
FEATURES
Access Times of 70, 90, 100, 120ns
Packaging
• 159 PBGA, 13x22mm – 1.27mm pitch
1,000,000 Erase/Program Cycles per sector
Page Mode
• Page size is 8 words: Fast page read access from
random locations within the page.
Sector Architecture
• Bank A (16Mb): 4Kw x 8 and 32 Kw x 31
• Bank B (48Mb): 32Kw x 96
• Bank C (48Mb): 32Kw x 96
• Bank D (16Mb): 4Kw x 8 and 3Kw x 31
Both top and bottom boot blocks
Zero Power Operation
Organized as 8Mx32, user configurable as 2x8Mx16
Commercial, Industrial and Military Temperature
Ranges
3.3 Volt for read, erase and write operations
Simultaneous read/write operations:
• Data can be continuously read from one bank
while executing erase/program functions in
another bank
• Zero latency between read and write operations
Erase Suspend/Resume
• Suspends erase operations to allow read or
programming in other sectors of same bank
Data Polling and Toggle Bits
• Provides a software method of detecting the status
of program or erase cycles
Unlock Bypass Program command
• Reduces overall programming time when issuing
multiple program command sequences
Ready/Busy# output (RY/BY#)
• Hardware method for detecting program or erase
cycle completion
Hardware reset pin (RESET#)
• Hardware method of resetting the internal state
machine to the read mode
WP#/ACC input pin
• Write protect (WP#) function allows protection of
two outermost boot sector, regardless of sector
protect status
• Acceleration (ACC) function accelerates program
timing
Persistent Sector Protection
• A command sector protection method of locking
combinations of individual sectors and sector
groups to prevent program or erase operation
within that sector
Password Sector Protection or Cancellation
• A sector protection method to lock combinations
of individual sectors and sector groups to prevent
program or erase operations within that sector
using a user-defined 64-bit password.
* This product is subject to change without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W78M32V-XBX pdf, 반도체, 판매, 대치품
White Electronic Designs
W78M32V-XBX
www.DataSheet4U.com
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is a latch used to store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device. Table 1 lists the device
bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
TABLE 1. DEVICE BUS OPERATION3
Operation
CS# OE# WE# RESET# WP#/ACC
Addresses
(A22-A0)
DQ15-DQ0
Read
L LH
H
X
AIN DOUT
Write
LHL
H
X
AIN DIN
Standby
VIO± X
X
VIO ±
X (Note 2)
X
High-Z
0.3 V 0.3 V
Output Disable
L HH
H
X
X High-Z
Reset
X XX
L
X
X High-Z
Temporary Sector Unprotect (High
Voltage
X X X VID
X
AIN DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In,
DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section.
2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
3. For each chip
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must drive
the OE# and appropriate CS# pins to VIL. CS# is the power
control. OE# is the output control and gates array data to
the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until
the command register contents are altered.
Refer to the AC Characteristics table for timing specifications
and to Figure 11 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable
addresses to valid output data. The chip enable access
time (tCS) is the delay from the stable addresses and stable
CS# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses
have been stable for at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. Address bits A22–A3 select an 8
word page, and address bits A2–A0 select a specific word
within that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is tACC or tCS and
subsequent page read accesses (as long as the locations
specified by the microprocessor falls within that page) is
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 3
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W78M32V-XBX 전자부품, 판매, 대치품
White Electronic Designs
W78M32V-XBX
www.DataSheet4U.com
Bank
TABLE 4. SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Sector Address (A22-A12)
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
00000001XXX
00000010XXX
00000011XXX
00000100XXX
00000101XXX
00000110XXX
00000111XXX
00001000XXX
00001001XXX
00001010XXX
00001011XXX
00001100XXX
00001101XXX
00001110XXX
00001111XXX
00010000XXX
00010001XXX
00010010XXX
00010011XXX
00010100XXX
00010101XXX
00010110XXX
00010111XXX
00011000XXX
00011001XXX
00011010XXX
00011011XXX
00011100XXX
00011101XXX
00011110XXX
00011111XXX
Sector Size (Kwords)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address Range (x16)
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 3
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W78M32V-XBX

8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package

White Electronic Designs
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