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BH616UV8010 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BH616UV8010은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 BH616UV8010 자료 제공

부품번호 BH616UV8010 기능
기능 Ultra Low Power/High Speed CMOS SRAM
제조업체 Brilliance Semiconductor
로고 Brilliance Semiconductor 로고


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BH616UV8010 데이터시트, 핀배열, 회로
Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BH616UV8010www.DataSheet4U.com
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.6V Operation current : 12mA (Max.)at 55ns
2mA (Max.)at 1MHz
Standby current : 2.5uA (Typ.) at 3.0V/25OC
VCC = 1.2V Data retention current : 1.2uA (Typ.) at 25OC
Ÿ High speed access time :
-55 55ns (Max.) at VCC=1.65~3.6V
-70 70ns (Max.) at VCC=1.65~3.6V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n POWER CONSUMPTION
n DESCRIPTION
The BH616UV8010 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 524,288 by 16 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25OC and maximum access time of 55ns at
1.65V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
(ICCSB1, Max)
VCC=3.6V VCC=1.8V
POWER DISSIPATION
1MHz
VCC=3.6V
10MHz
Operating
(ICC, Max)
fMax.
1MHz
VCC=1.8V
10MHz
fMax.
PKG TYPE
BH616UV8010DI
DICE
BH616UV8010AI
Industrial
-40OC to +85OC
15uA
12uA
2mA
6mA 12mA 1.5mA 5mA
8mA BGA-48-0608
BH616UV8010TI
TSOP I-48
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE 11
CE2 12
NC 13
UB 14
LB 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
BH616UV8010TI
123456
A LB OE A0 A1 A2 CE2
B DQ8 UB A3 A4 CE1 DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D VSS DQ11 A17 A7 DQ3 VCC
E VCC DQ12 VSS A16 DQ4 VSS
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 NC A12 A13 WE DQ7
H A18 A8 A9 A10 A11 NC
48 A16
47 NC
46 VSS
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 VSS
26 CE1
25 A0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
DQ0
.
.
.
.
.
.
DQ15
CE2
CE1
WE
OE
UB
LB
VCC
VSS
Address
Input
Buffer
10
. 16
.
.
. 16
.
.
Control
Row
Decoder
1024
Memory Array
1024 x 8192
Data
Input
Buffer
Data
Output
Buffer
16
16
8192
Column I/O
Write Driver
Sense Amp
512
Column Decoder
9
Address Input Buffer
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
1
Revision 1.2
May.
2006




BH616UV8010 pdf, 반도체, 판매, 대치품
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
BH616UV8010www.DataSheet4U.com
SYMBOL
VDR
ICCDR
tCDR
tR
PARAMETER
TEST CONDITIONS
VCC for Data Retention
CE1VCC-0.2V or CE20.2V,
VINVCC-0.2V or VIN0.2V
Data Retention Current
CE1VCC-0.2V or CE20.2V,
VINVCC-0.2V or VIN0.2V
Chip Deselect to Data
Retention Time
See Retention Waveform
Operation Recovery Time
VCC=1.2V
MIN.
1.0
--
0
tRC (2)
1. Typical characteristics are at TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
TYP. (1)
--
1.2
--
--
MAX. UNITS
-- V
7.0 uA
-- ns
-- ns
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
VCC
CE1
VCC
tCDR
VIH
Data Retention Mode
VDR1.0V
CE1VCC - 0.2V
VCC
tR
VIH
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
VCC
tCDR
Data Retention Mode
VDR1.0V
CE2
CE20.2V
VIL
VCC
tR
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
VCC / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
Output Load
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1,
tCHZ2, tBDO, tOHZ, tWHZ, tOW
Others
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
ALL INPUT PULSES
90%
10%
→←
Rise Time:
1V/ns
90%
10%
→←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM HTO L
MAY CHANGE
FROM LTO H
DONT CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM HTO L
WILL BE CHANGE
FROM LTO H
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
OFFSTATE
R0201-BH616UV8010
4
Revision 1.2
May.
2006

4페이지










BH616UV8010 전자부품, 판매, 대치품
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
BH616UV8010www.DataSheet4U.com
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tWC
tAVWL
tAS
tAVWH
tAW
tELWH
tCW
tBLWH
tBW
tWLWH
tWP
tWHAX
tWR1
tE2LAX
tWR2
tWLQZ
tWHZ
tDVWH
tDW
tWHDX
tDH
tGHQZ
tOHZ
tWHQX
tOW
DESCRIPTION
CYCLE TIME : 55ns CYCLE TIME : 70ns
MIN. TYP. MAX. MIN. TYP. MAX.
Write Cycle Time
55 --
-- 70 --
--
Address Set up Time
0 -- -- 0 -- --
Address Valid to End of Write
45 --
-- 60 --
--
Chip Select to End of Write
Data Byte Control to End of Write
45
(LB, UB) 45
--
--
-- 60 --
-- 60 --
--
--
Write Pulse Width
Write Recovery Time
35
(CE1, WE) 0
--
--
-- 35 --
-- 0 --
--
--
Write Recovery Time
(CE2) 0 -- -- 0 -- --
Write to Output High Z
-- -- 20 -- -- 25
Data to Write Time Overlap
25 --
-- 30 --
--
Data Hold from Write Time
0 -- -- 0 -- --
Output Disable to Output in High Z
-- -- 25 -- -- 30
End of Write to Output Active
5 -- -- 5 -- --
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
ADDRESS
tWC
OE
CE1
tCW(11)
(5)
tWR1(3)
CE2
LB, UB
WE
DOUT
DIN
R0201-BH616UV8010
(5)
tCW(11)
tBW
tWR2(3)
tAS
tOHZ(4,10)
tAW
tWP(2)
tDH
tDW
7
Revision 1.2
May.
2006

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