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PDF ADP5022 Data sheet ( Hoja de datos )
| Número de pieza | ADP5022 | |
| Descripción | 600 mA Buck Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP5022 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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Dual 3 MHz, 600 mA Buck
Regulator with 150 mA LDO
ADP5022
FEATURES
Input voltage range: 2.4 V to 5.5 V
Tiny 16-ball, 2 mm × 2 mm WLCSP package
Overcurrent and thermal protection
Soft start
Factory programmable undervoltage lockout on VDDA
system supply of either 2.2 V or 3.9 V
Factory programmable default output voltages for all
3 channels
www.DBautcakS1heaentd4UB.uccokm2 key specifications
Current mode architecture for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Forced PWM and auto PWM/PSM modes
Out-of-phase operation for reduced input filtering
100% duty cycle low dropout mode
24 μA typical quiescent current per channel, no switching
LDO key specifications
Stable with 1 μF ceramic output capacitors
High PSRR
60 dB up to 10 KHz
Low output noise
65 μV rms output noise at VOUT3 = 3.3 V
Low dropout voltage: 150 mV @ 150 mA load
11 μA typical ground current at no load
APPLICATIONS
USB devices
Handheld products
Multivoltage power for processors, ASICS, FPGAs,
and RF chipsets
GENERAL DESCRIPTION
The ADP5022 is a micro power management unit (micro PMU)
that combines two high performance buck regulators and a low
dropout regulator (LDO) in a tiny 16-ball 2.08 mm × 2.08 mm
WLCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables
tiny multilayer external components and minimizes the board
space required. When the MODE pin is set high, the buck reg-
ulators operate in forced PWM mode. When the MODE pin is
set low, the buck regulators automatically switch operating
modes, depending on the load current level. At higher output
loads, the buck regulators operate in PWM mode. When the
load current falls below a predefined threshold, the regulators
operate in power save mode (PSM), improving the light-load
efficiency.
The two bucks operate out-of-phase to reduce the input
capacitor requirement and noise.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5022 LDO extends the battery life of
portable devices. The LDO maintains power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator in the ADP5022 has a dedicated, independent
enable pin. A high voltage level applied to the enable pin activates
the respective regulator. The default output voltages are factory
programmable and can be set to a wide range of options.
VIN = 2.4V
TO 5.5V
C1
1µF
C2
4.7µF
C3
4.7µF
ADP5022
ON
OFF
VIN1
EN1
VIN2
ON
OFF
EN2
VDDA
ON
OFF
VIN3
EN3
BUCK1
EN_BK1
MODE
MODE
BUCK2
EN_BK2
LDO1
EN_LDO1
SW1
VOUT1
PGND1
MODE
SW2
VOUT2
PGND2
VOUT3
AGND
Figure 1. Typical Applications Circuit
L1
1µH
VOUT1 @
C4 600mA
10µF
PWM
L2 PWM/PSM
1µH
VOUT2 @
C5 600mA
10µF
VOUT3 @
150mA
C6
1µF
COUT_3
C1
C3 C4
C2
5.0mm
L1 COUT_1 COUT_2
4.7mm
Figure 2. Typical PCB Layout
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
ADP5022
LDO SPECIFICATIONS
VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0.5 V) or 2.3 V, whichever is greater, VIN3 ≤ VIN1, IOUT3 = 10 mA; CIN3 = COUT3 =
1 μF, TJ = −40°C to +125°C, unless otherwise noted.1
Table 3.
Parameter
OPERATING SUPPLY CURRENT2
OUTPUT VOLTAGE ACCURACY
REGULATION
www.DatLainSeheReetg4uUl.actioomn
Load Regulation3
DROPOUT VOLTAGE4
START-UP TIME5
From Shutdown State
CURRENT-LIMIT THRESHOLD6
OUTPUT NOISE
POWER SUPPLY REJECTION RATIO
Symbol
IVIN3-GND
VOUT3
Test Conditions/Comments
IOUT3 = 0 μA
IOUT3 = 10 mA
IOUT3 = 150 mA
100 μA < IOUT3 < 150 mA,
VIN3 = (VOUT3 + 0.5 V) to 5.5 V
Min Typ Max Unit
11 21
16 29
31 43
μA
μA
μA
−2 +2 %
∆VOUT3/∆VIN3 VIN3 = (VOUT3 + 0.5 V) to 5.5 V, IOUT = 1 mA −0.03
+0.03 %/ V
∆VOUT3/∆IOUT3 IOUT3 = 1 mA to 150 mA
0.002 0.0075 %/mA
VDROPOUT
VOUT3 = 3.0 V, IOUT3 = 10 mA
VOUT3 = 3.0 V, IOUT3 = 150 mA
7
110 150
mV
mV
TSTARTUP3-SD
ILIMIT3
OUTNOISE
PSRR
200
160 240 350
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 Hz to 100 kHz, VIN3= 5 V, VOUT3 = 2.4 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.2 V
65
52
40
10 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 kHz, VIN3 = 5 V, VOUT3 = 2.3 V
10 kHz, VIN3 = 5 V, VOUT3 = 1.2 V
60
66
70
μs
mA
μV rms
μV rms
μV rms
dB
dB
dB
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control.
2 LDO operating supply current is the current drawn from VIN3 to AGND when the LDO is enabled. Whenever any regulator channel is enabled, current is drawn from
VIN1 to AGND. This current is 8 μA typical and is included in the IGND1, IGND2, and IGND1-2 specifications.
3 Based on an end-point calculation using 1 mA and 150 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
5 Start-up time is defined as the time between the rising edge of EN3 to VOUT3 being at 90% of its nominal value.
6 Current-limit threshold is defined as the current at which VOUT3 drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is
defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
Rev. A | Page 5 of 28
5 Page 
T
VOUT
1
ISW
2
SW
4
CH1 50.0V BW CH2 500mA Ω M 4.00µs A CH2
CH4 2.00V BW
T 28.40%
240mA
www.DatFaigSuhree e22t4. TUy.pcicoaml Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
T
VOUT
1
ISW
2
SW
4
CH1 50.0V BW CH2 500mA Ω M 4.00µs A CH2
CH4 2.00V BW
T 28.40%
220mA
Figure 23. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode
T
VOUT
1
ISW
2
SW
4
CH1 50mV BW CH2 500mA Ω M 400ns A CH2
CH4 2.00V BW
T 28.40%
220mA
Figure 24. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
T
VOUT
1
ISW
2
SW
ADP5022
4
CH1 50mV BW CH2 500mA Ω M 400ns A CH2
CH4 2.00V BW
T 28.40%
220mA
Figure 25. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
T
VIN
VOUT
1
SW
3
CH1 50.0mV BW
M 1.00ms
CH3 1.00V BW CH4 2.00V BW
T 30.40%
A CH3
4.80V
Figure 26. Buck1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, VOUT1 = 3.3 V, PWM Mode
T
VIN
VOUT
1
SW
43
CH1 50.0mV BW
M 1.00ms
CH3 1.00V BW CH4 2.00V BW
T 30.40%
A CH3
4.80V
Figure 27. Buck2 Response to Line Transient, VIN = 4.5 V to 5.0 V,
VOUT2 = 1.8 V, PWM Mode
Rev. A | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADP5022.PDF ] | |
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