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부품번호 PCA9502 기능
기능 8-bit I/O expander
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PCA9502 데이터시트, 핀배열, 회로
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Rev. 03 — 13 October 2006
Product data sheet
1. General description
www.2Da.taShFeeeta4Ut.ucormes
The PCA9502 is an 8-bit I/O expander with I2C-bus/SPI host interface. The device comes
in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery
operated applications.
The device also supports software reset, which allows the host to reset the device at any
time, independent of the hardware reset signal.
2.1 General features
I Selectable I2C-bus or SPI interface
I 3.3 V or 2.5 V operation
I Industrial temperature range: 40 °C to +85 °C
I Eight programmable I/O pins
I Software reset
I Industrial and commercial temperature ranges
I Available in HVQFN24 package
I 16 hardware-selectable slave addresses
2.2 I2C-bus features
I Noise filter on SCL/SDA inputs
I 400 kbit/s (maximum)
I Compliant with I2C-bus Fast-mode
I Slave mode only
2.3 SPI features
I 15 Mbit/s maximum speed
I Slave mode only
I SPI Mode 0
3. Applications
I Factory automation and process control
I Portable and battery operated devices
I Cellular data devices




PCA9502 pdf, 반도체, 판매, 대치품
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
www.DataSheet4U.com
Table 2.
Symbol
IRQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
VSS
VSS
Pin description …continued
Pin Type Description
12 O Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the I/O Interrupt Enable register
(IOIntEna). The interrupt condition is the change of state of the
input pins. An external resistor (1 kfor 3.3 V, 1.5 kfor 2.5 V)
must be connected between this pin and VDD.
13 I/O programmable I/O pin
14 I/O programmable I/O pin
15 I/O programmable I/O pin
16 I/O programmable I/O pin
18 I/O programmable I/O pin
19 I/O programmable I/O pin
20 I/O programmable I/O pin
21 I/O programmable I/O pin
10, 17, -
23
ground
center -
pad
The center pad on the back side of the HVQFN24 package is
metallic and should be connected to ground on the printed-circuit
board.
[1] See Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset”
7. Functional description
The device interfaces to a host through either I2C-bus or SPI interface (selectable through
I2C/SPI pin), and provides the host with eight programmable GPIO pins.
7.1 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 3.
Table 3 summarizes the state of registers after reset.
Table 3. Registers after reset
Register
Reset state
I/O direction
all bits cleared
I/O interrupt enable
all bits cleared
I/O control
all bits cleared
Table 4 summarizes the state of hardware pins after reset.
Table 4.
Signal
I/Os
IRQ
Signals after reset
Reset state
inputs
HIGH by external pull-up
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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PCA9502 전자부품, 판매, 대치품
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
9. I2C-bus operation
The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
9.1
www.DataSheet4U.com
Data transfers
One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see Figure 5). The bus is considered to be busy after the START condition and
free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
SDA
SCL
data line
stable;
data valid
Fig 4. Bit transfer on the I2C-bus
change
of data
allowed
mba607
SDA
SDA
SCL
S
START condition
P
STOP condition
SCL
mba608
Fig 5. START and STOP conditions
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit.
(see Figure 6). The clock pulse related to the acknowledge bit is generated by the master.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse, while the transmitting device releases this pulse (see Figure 7).
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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