LP2994M 데이터시트 PDF

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부품번호 LP2994M 기능
기능 DDR Termination Regulator
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LP2994M 데이터시트, 핀배열, 회로
May 2002
DDR Termination Regulator
General Description
The LP2994 regulator is designed to provide a linear solution
to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se-
ries Stub Termination Logic) for active termination of DDR-
SDRAM. The device utilizes an internal operational amplifier
to provide linear regulation of VTT without the need for
expensive external components. The output stage prevents
shoot through while delivering 1.5A continuous current and
maintaining excellent load regulation. The LP2994 also in-
corporates an active low shutdown pin to tri-state the output
during Suspend To Ram (STR) states.
Patents Pending
n Source and sink current
n Low external component count
n Independent analog and power rails
n Linear topology
n Small package SO-8
n Low cost and easy to use
n Shutdown pin
n SSTL-2
n SSTL-3
n DDR-SDRAM Termination
n DDR-II Termination
Typical Application Circuit
FIGURE 1. SSTL-2 VTT Termination
© 2002 National Semiconductor Corporation DS200459

LP2994M pdf, 반도체, 판매, 대치품
Typical Performance Characteristics
Iq vs VIN (25˚C)
Iq vs VIN (0, 25, and 125˚C)
Iq vs Temperature ( VIN = 2.5V)
ISD vs VIN (25˚C)
ISD vs VIN (0, 25, and 125˚C)
ISD vs Temperature ( VIN = 2.5V)


LP2994M 전자부품, 판매, 대치품
Block Diagram
The LP2994 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
output, VTT is capable of sinking and sourcing current while
regulating the output voltage equal to VDDQ / 2. The output
stage has been designed to maintain excellent load regula-
tion while preventing shoot through. The LP2994 also incor-
porates two distinct power rails which separates the analog
circuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipa-
tion. It also permits the LP2994 to provide a termination
solution for the next generation of DDR-SDRAM memory
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termina-
tion. This involves one RS series resistor from the chipset to
the memory and one RT termination resistor. Typical values
for RS and RT are 25 Ohms, although these can be changed
to scale the current requirements from the LP2994. This
implementation can be seen below in Figure 2.
FIGURE 2. SSTL Termination Scheme


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DDR Termination Regulator

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DDR Termination Regulator

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