LP2994MX 데이터시트 PDF

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May 2002

LP2994

DDR Termination Regulator

General Description

The LP2994 regulator is designed to provide a linear solution

to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se-

ries Stub Termination Logic) for active termination of DDR-

SDRAM. The device utilizes an internal operational amplifier

to provide linear regulation of VTT without the need for

expensive external components. The output stage prevents

shoot through while delivering 1.5A continuous current and

maintaining excellent load regulation. The LP2994 also in-

corporates an active low shutdown pin to tri-state the output

during Suspend To Ram (STR) states.

Patents Pending

Features

n Source and sink current

n Low external component count

n Independent analog and power rails

n Linear topology

n Small package SO-8

n Low cost and easy to use

n Shutdown pin

Applications

n SSTL-2

n SSTL-3

n DDR-SDRAM Termination

n DDR-II Termination

Typical Application Circuit

FIGURE 1. SSTL-2 VTT Termination

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Typical Performance Characteristics

Iq vs VIN (25˚C)

Iq vs VIN (0, 25, and 125˚C)

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Iq vs Temperature ( VIN = 2.5V)

ISD vs VIN (25˚C)

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ISD vs VIN (0, 25, and 125˚C)

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ISD vs Temperature ( VIN = 2.5V)

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Block Diagram

Description

The LP2994 is a linear bus termination regulator designed to

meet the JEDEC requirements of SSTL-2 and SSTL-3. The

output, VTT is capable of sinking and sourcing current while

regulating the output voltage equal to VDDQ / 2. The output

stage has been designed to maintain excellent load regula-

tion while preventing shoot through. The LP2994 also incor-

porates two distinct power rails which separates the analog

circuitry from the power output stage. This allows a split rail

approach to be utilized to decrease internal power dissipa-

tion. It also permits the LP2994 to provide a termination

solution for the next generation of DDR-SDRAM memory

(DDRII).

Series Stub Termination Logic (SSTL) was created to im-

prove signal integrity of the data transmission across the

memory bus. This termination scheme is essential to prevent

data error from signal reflections while transmitting at high

frequencies encountered with DDR-SDRAM. The most com-

mon form of termination is Class II single parallel termina-

tion. This involves one RS series resistor from the chipset to

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the memory and one RT termination resistor. Typical values

for RS and RT are 25 Ohms, although these can be changed

to scale the current requirements from the LP2994. This

implementation can be seen below in Figure 2.

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FIGURE 2. SSTL Termination Scheme

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