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부품번호 | QL3025 기능 |
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기능 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | ||
제조업체 | QuickLogic Corporation | ||
로고 | |||
전체 17 페이지수
QL3025 pASIC 3 FPGA Data Sheet
• • • • • • 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
• 25,000 Usable PLD Gates with 204 I/Os
www.Da•taS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Four Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Two global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 204 I/O Pins
• 196 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Four High Drive input-only pins
• Four High Drive input-only/distributed
network pins
Figure 1: 672 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Symbol
Parameter
Table 3: Clock Cells
Propagation Delays (ns) Loads per Half Column a
1 2 3 4 8 10 11
tACK
Array Clock Delay
1.2 1.2 1.3 1.3 1.5 1.6 1.7
tGCKP
Global Clock Pin Delay
0.7 0.7 0.7 0.7 0.7 0.7 0.7
tGCKB Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-
bal clock has up to 11 loads per half column.
www.DataSheet4U.com
Symbol
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Table 4: Input-Only I/O Cells
Parameter
Propagation Delays (ns) Fanout a
1 2 3 4 8 10
Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.7 1.0 1.2 1.5 2.5 3.0
Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in Table 7.
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© 2002 QuickLogic Corporation
4페이지 QL3025 pASIC 3 FPGA Data Sheet Rev E
Table 8: DC Characteristics
Symbol
Parameter
Conditions
Min Max Units
VIH
VIL
VOH
VOL
II
www.DataSheet4U.comIOZ
CI
IOS
ICC
ICCIO
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
I or I/O Input Leakage Current
3-State Output Leakage Current
Input Capacitanceb
Output Short Circuit Currentc
D.C. Supply Currentd
D.C. Supply Current on VCCIO
IOH = -12 mA
IOH = -500 µA
IOL = 16 mAa
IOL = 1.5 mA
VI = VCCIO or GND
VI = VCCIO or GND
VO = GND
VO = VCC
VI, VIO = VCCIO or GND
0.5 VCC
-0.5
2.4
VCCIO + 0.5
0.3 VCC
0.9 VCC
0.45
0.1 VCC
-10 10
-10 10
10
-15 -180
40 210
0.50 (typ)
2
0 100
V
V
V
V
V
V
µA
µA
pF
mA
mA
mA
µA
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All
other devices have 8 mA IOL specifications.
b. Capacitance is sample tested only. Clock pins are 12 pF maximum.
c. Only one output at a time. Duration should not exceed 30 seconds.
d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all
industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLog-
ic customer applications group. (See Contact Information).
© 2002 QuickLogic Corporation
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www.quicklogic.com ••
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QL3025 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | QuickLogic Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |