QL3060 Datasheet PDF - QuickLogic Corporation
| Part Number | QL3060 | |
| Description | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | |
| Manufacturers | QuickLogic Corporation | |
| Logo |  |
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There is a preview and QL3060 download ( pdf file ) link at the bottom of this page. Total 19 Pages | ||
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QL3060 pASIC 3 FPGA Data Sheet
• • • • • • 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
• 60,000 Usable PLD Gates with 316 I/Os
www.Da•taS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Six global clock/control networks available
to the logic cell F1, clock set, and reset
inputs and the input and I/O register clock,
reset, and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 316 I/O Pins
• 308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Eight high-drive input/distributed
network pins
Figure 1: 1,584 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3060 pASIC 3 FPGA Data Sheet Rev D
Table 5: Output-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Output Load
Capacitance (pF)
30 50 75 100 150
tOUTLH
Output Delay Low to High
2.1 2.5 3.1
tOUTHL
Output Delay High to Low
2.2 2.6 3.2
tPZH Output Delay Tri-state to High 1.2 1.7 2.2
tPZL
Output Delay Tri-state to Low
1.6
2.0
2.6
tPHZ Output Delay High to Tri-State a 2.0
-
-
tPLZ Output Delay Low to Tri-State 1.2
-
-
3.6
3.7
2.8
3.1
-
-
4.7
4.8
3.9
4.2
-
-
www.DataSheet4U.coam. The loads presented in Figure 2 are used for tPXZ:
1ΚΩ
tPHZ
5 pF
1ΚΩ
tPLZ
5 pF
Figure 2: Loads used for tPXZ
© 2002 QuickLogic Corporation
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www.quicklogic.com ••
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for QL3060 electronic component. |
| Information | Total 19 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ QL3060.PDF Datasheet ] | |
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