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PDF QL3040 Data sheet ( Hoja de datos )
| Número de pieza | QL3040 | |
| Descripción | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | |
| Fabricantes | QuickLogic Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de QL3040 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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QL3040 pASIC 3 FPGA Data Sheet
• • • • • • 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
• 40,000 Usable PLD Gates with 252 I/Os
www.Da•taS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Six global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 252 I/O Pins
• 244 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Eight high-drive input/distributed
network pins
Figure 1: 1,008 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Table 5: Output-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Output Load
Capacitance (pF)
30 50 75 100 150
tOUTLH
Output Delay Low to High
2.1
tOUTHL
Output Delay High to Low
2.2
tPZH Output Delay Tri-state to High 1.2
tPZL
Output Delay Tri-state to Low
1.6
tPHZ Output Delay High to Tri-State a 2.0
tPLZ
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Output Delay Low to Tri-State 1.2
a. The loads presented in Figure 2 are used for tPXZ:
2.5
2.6
1.7
2.0
-
-
3.1
3.2
2.2
2.6
-
-
3.6
3.7
2.8
3.1
-
-
4.7
4.8
3.9
4.2
-
-
1ΚΩ
tPHZ
5 pF
1ΚΩ
tPLZ
5 pF
Figure 2: Loads used for tPXZ
© 2002 QuickLogic Corporation
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www.quicklogic.com ••
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5 Page 
QL3040 pASIC 3 FPGA Data Sheet Rev E
The 1149.1 standard requires the following three tests:
www.DataSheet4U.com
• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload
Instruction), and input boundary cells capture the input data for analysis.
• Sample/Preload Instruction. This instruction allows a device to remain in its
functional mode, while selecting the boundary scan register to be connected between
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a
data scan operation, allowing users to sample the functional data entering and leaving
the device.
• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary
scan entirely, so the data passes through the bypass register. The Bypass instruction
allows users to test a device without passing through other devices. The bypass register
is connected between the TDI and TDO pins, allowing serial data to be transferred
through a device without affecting the operation of the device.
© 2002 QuickLogic Corporation
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www.quicklogic.com ••
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11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet QL3040.PDF ] | |
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