QL3004E Datasheet PDF - QuickLogic Corporation
| Part Number | QL3004E | |
| Description | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | |
| Manufacturers | QuickLogic Corporation | |
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There is a preview and QL3004E download ( pdf file ) link at the bottom of this page. Total 18 Pages | ||
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4,000 Usable PLD Gates with 82 I/Os
www.DataSh3e0e0t4UM.cHomz 16-bit Counters,
400 MHz Datapaths
0.35 µm four-layer metal non-volatile CMOS
process for smallest die sizes
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100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
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Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
Two global clock/control networks available
to the logic cell; F1, clock, set and reset
inputs and the data input, I/O register clock,
reset and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
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Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
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Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
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74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Four High-Drive input-only pins
Four High-Drive/distributed network pins
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Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.7 1.0 1.2 1.5 2.5 3.0
Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0
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Output Delay Low to High
2.1 2.5 3.1
3.6
4.7
Output Delay High to Low
2.2 2.6 3.2
3.7
4.8
Output Delay Tri-state to High 1.2 1.7 2.2
2.8
3.9
Output Delay Tri-state to Low
1.6
2.0
2.6
Output Delay High to Tri-State a 2.0
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Output Delay Low to Tri-State 1.2
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Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for QL3004E electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ QL3004E.PDF Datasheet ] | |
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