LP2997 - DDR-II Termination Regulator

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LP2997 기능

기능

DDR-II Termination Regulator

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National Semiconductor

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June 2004

LP2997

DDR-II Termination Regulator

General Description

The LP2997 linear regulator is designed to meet the JEDEC

SSTL-18 specifications for termination of DDR-II memory.

The device contains a high-speed operational amplifier to

provide excellent response to load transients. The output

stage prevents shoot through while delivering 500mA con-

tinuous current and transient peaks up to 900mA in the

application as required for DDR-II SDRAM termination. The

LP2997 also incorporates a VSENSE pin to provide superior

load regulation and a VREF output as a reference for the

chipset and DIMMs.

An additional feature found on the LP2997 is an active low

shutdown (SD) pin that provides Suspend To RAM (STR)

functionality. When SD is pulled low the VTT output will

tri-state providing a high impedance output, but, VREF will

remain active. A power savings advantage can be obtained

in this mode through lower quiescent current.

Features

n Source and sink current

n Low output voltage offset

n No external resistors required

n Linear topology

n Suspend to Ram (STR) functionality

n Low external component count

n Thermal Shutdown

n Available in SO-8, PSOP-8 packages

Applications

n DDR-II Termination Voltage

n SSTL-18 Termination

Typical Application Circuit

20109418

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Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C and limits in boldface type

apply over the full Operating Temperature Range (TJ = 0˚C to +125˚C) (Note 4). Unless otherwise specified,

AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. (Continued)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The

guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed

test conditions.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2˚ C/W

junction to ambient with no heat sink.

Note 4: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control

(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 5: Quiescent current defined as the current flow into AVIN.

Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA, and

the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal

shutdown.

Note 7: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.

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Block Diagram

Description

The LP2997 is a linear bus termination regulator designed to

meet the JEDEC requirements of SSTL-18. The output, VTT

is capable of sinking and sourcing current while regulating

the output voltage equal to VDDQ / 2. The output stage has

been designed to maintain excellent load regulation while

preventing shoot through. The LP2997 also incorporates two

distinct power rails that separates the analog circuitry from

the power output stage. This allows a split rail approach to

be utilized to decrease internal power dissipation. It also

permits the LP2997 to provide a termination solution for the

next generation of DDR-SDRAM memory (DDRII).

Pin Descriptions

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the LP2997.

AVIN is used to supply all the internal control circuitry. PVIN,

however, is used exclusively to provide the rail voltage for

the output stage used to create VTT. These pins have the

capability to work off separate supplies, under the condition

that AVIN is always greater than or equal to PVIN. For

SSTL-18 applications, it is recommended to connect PVIN to

the 1.8V rail used for the memory core and AVIN to a rail

within its operating range of 2.2V to 5.5V (typically a 2.5V

supply). PVIN should always be used with either a 1.8V or

2.5V rail. This prevents the thermal limit from tripping be-

cause of excessive internal power dissipation. If the junction

temperature exceeds the thermal shutdown than the part will

enter a shutdown state identical to the manual shutdown

where VTT is tri-stated and VREF remains active. A lower rail

such as 1.5V can be used but it will reduce the maximum

output current, therefore it is not recommended for most

termination schemes.

VDDQ

VDDQ is the input used to create the internal reference

voltage for regulating VTT. The reference voltage is gener-

ated from a resistor divider of two internal 50kΩ resistors.

This guarantees that VTT will track VDDQ / 2 precisely. The

optimal implementation of VDDQ is as a remote sense. This

can be achieved by connecting VDDQ directly to the 1.8V

rail at the DIMM instead of PVIN. This ensures that the

reference voltage tracks the DDR memory rails precisely

without a large voltage drop from the power lines. For

SSTL-18 applications VDDQ will be a 1.8V signal, which will

20109405

create a 0.9V termination voltage at VTT (See Electrical

Characteristics Table for exact values of VTT over tempera-

ture).

VSENSE

The purpose of the sense pin is to provide improved remote

load regulation. In most motherboard applications the termi-

nation resistors will connect to VTT in a long plane. If the

output voltage was regulated only at the output of the

LP2997 then the long trace will cause a significant IR drop

resulting in a termination voltage lower at one end of the bus

than the other. The VSENSE pin can be used to improve this

performance, by connecting it to the middle of the bus. This

will provide a better distribution across the entire termination

bus. If remote load regulation is not used then the VSENSE

pin must still be connected to VTT. Care should be taken

when a long VSENSE trace is implemented in close proximity

to the memory. Noise pickup in the VSENSE trace can cause

problems with precise regulation of VTT. A small 0.1uF ce-

ramic capacitor placed next to the VSENSE pin can help filter

any high frequency signals and preventing errors.

SHUTDOWN

The LP2997 contains an active low shutdown pin that can be

used for suspend to RAM functionality. In this condition the

VTT output will tri-state while the VREF output remains active

providing a constant reference signal for the memory and

chipset. During shutdown VTT should not be exposed to

voltages that exceed PVIN. With the shutdown pin asserted

low the quiescent current of the LP2997 will drop, however,

VDDQ will always maintain its constant impedance of 100kΩ

for generating the internal reference. Therefore, to calculate

the total power loss in shutdown both currents need to be

considered. For more information refer to the Thermal Dis-

sipation section. The shutdown pin also has an internal

pull-up current; therefore, to turn the part on the shutdown

pin can either be connected to AVIN or left open

VREF

VREF provides the buffered output of the internal reference

voltage VDDQ / 2. This output should be used to provide the

reference voltage for the Northbridge chipset and memory.

Since these inputs are typically an extremely high imped-

ance, there should be little current drawn from VREF. For

improved performance, an output bypass capacitor can be

used, located close to the pin, to help with noise. A ceramic

capacitor in the range of 0.1 µF to 0.01 µF is recommended.

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