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PDF MPC8533E Data sheet ( Hoja de datos )
| Número de pieza | MPC8533E | |
| Descripción | PowerQUICC III Integrated Processor Hardware Specifications | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
Document Number: MPC8533EEC
Rev. 3, 11/2009
MPC8533E PowerQUICC™ III
Integrated Processor
Hardwarewww.DataSheet4U.com Specifications
1 MPC8533E Overview
This section provides a high-level overview of MPC8533E
features. Figure 1 shows the major functional units within
the device.
1.1 Key Features
The following list provides an overview of the device feature
set:
• High-performance 32-bit Book E–enhanced core
built on Power Architecture™ technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
Contents
1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Enhanced Three-Speed Ethernet (eTSEC),
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9. Ethernet Management Interface Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. Programmable Interrupt Controller . . . . . . . . . . . . . 51
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 78
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
21. System Design Information . . . . . . . . . . . . . . . . . . 102
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 111
23. Document Revision History . . . . . . . . . . . . . . . . . . 114
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
1 page  
MPC8533E Overview
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
• Two enhanced three-speed Ethernet controllers (eTSECs)
— Three-speed support (10/100/1000 Mbps)
— Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, and
IEEE 802.3ab-compliant controllers
— Support for various Ethernet physical interfaces:
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII.
– 10/100 Mbps full- and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII.
www.DataSheet—4U.cFolmexible configuration for multiple PHY interface configurations.
— TCP/IP acceleration and QoS features available
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
– Supported in all FIFO modes
— Quality of service support:
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE Std 802.1™ virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound frames
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
– Up to 16 exact-match MAC addresses supported
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
5
5 Page 
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8533E.
B/G/L/OVDD + 20%
B/G/L/OVDD + 5%
VIH B/G/L/OVDD
www.DataSheet4U.com
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
Notes:
of tCLOCK1
1. tCLOCK refers to the clock period associated with the respective interface:
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references EC_GTX_CLK125.
For LBIU, tCLOCK references LCLK.
For PCI, tCLOCK references PCI_CLK or SYSCLK.
2. Please note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in Section 4.2.2.3 of the PCI 2.2 Local Bus Specifications.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD/TVDD
The core voltage must always be provided at nominal 1.0 V (see Table 2 for actual recommended core
voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must
be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the
associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy
appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential
receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for
the SSTL2 electrical signaling standard.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
11
11 Page | ||
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| PDF Descargar | [ Datasheet MPC8533E.PDF ] | |
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