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부품번호 K4T1G164QE 기능
기능 1Gb E-die DDR2 SDRAM
제조업체 Samsung Electronics
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K4T1G164QE 데이터시트, 핀배열, 회로
K4T1G044QE
K4T1G084QE
K4T1G164QE
DDR2 SDRAM
1Gb E-die DDR2 SDRAM Specification
60FBGA & 84FBGA with Lead-Free & Halogen-Free
www.DataSheet4U.com
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.1 December 2008




K4T1G164QE pdf, 반도체, 판매, 대치품
K4T1G044QE
K4T1G084QE
K4T1G164QE
DDR2 SDRAM
1.0 Ordering Information
Org.
256Mx4
128Mx8
64Mx16
DDR2-800 5-5-5
K4T1G044QE-HC(L)E7
K4T1G084QE-HC(L)E7
K4T1G164QE-HC(L)E7
DDR2-800 6-6-6
K4T1G044QE-HC(L)F7
K4T1G084QE-HC(L)F7
K4T1G164QE-HC(L)F7
DDR2-667 5-5-5
K4T1G044QE-HC(L)E6
K4T1G084QE-HC(L)E6
K4T1G164QE-HC(L)E6
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
4. “C” of Part number(13th digit) stands normal, and “L” stands for Low power products.
Package
60 FBGA
60 FBGA
84 FBGA
2.0 Key Features
Speed
CAS Latency
www.DattRaCShDe(metin4)U.com
tRP(min)
tRC(min)
DDR2-800 5-5-5
5
12.5
12.5
57.5
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/
pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x
8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x8) device receive 14/
10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in
84ball FBGA(x16).
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95 °C
• All of products are Lead-Free, Halogen-Free, and RoHS com-
pliant
Note : The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
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Rev. 1.1 December 2008

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K4T1G164QE 전자부품, 판매, 대치품
K4T1G044QE
K4T1G084QE
K4T1G164QE
DDR2 SDRAM
3.3 x16 package pinout (Top View) : 84ball FBGA Package
1 2 3 456 7 8 9
A
B
C
D
E
F
G
H
www.DataSheet4U.comJ
K
L
M
N
P
R
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
BA2
VSS
VDD
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10/AP
A3
A7
A12
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
Note : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD,
VDDQ, VSS, and VSSQ.
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7 of 45
Rev. 1.1 December 2008

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