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PDF M69KB128AB Data sheet ( Hoja de datos )
| Número de pieza | M69KB128AB | |
| Descripción | Burst PSRAM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M69KB128AB
128 Mbit (8Mb x16) 1.8V Supply, Burst PSRAM
Preliminary Data
Feature summary
■ Supply Voltage
– VCC = 1.7 to 1.95V core supply voltage
– VCCQ = 1.7 to VCC for I/O buffers
■ User-selectable Operating Modes
www.DataShe–et4AUs.cyonmchronous Modes: Random Read, and
Write, Page Read
– Synchronous Modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
■ Asynchronous Random Read
– Access Times: 70ns
■ Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
■ Burst Read
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 80 and
104MHz
– Output delay: 7ns at 104MHz
■ Low Power Consumption
– Active Current: < 25mA
– Standby Current: 200µA
– Deep Power-Down Current: 10µA
■ Low Power Features
– Partial Array Self Refresh (PASR)
– Deep Power-Down (DPD) Mode
■ Operating Temperature
– –30°C to +85°C
Wafer
M69KB128AB IS ONLY AVAILABLE AS PART
OF A MULTI-CHIP PACKAGE
July 2006
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/64
www.st.com
1
1 page  
M69KB128AB
List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Page mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Operating Frequency versus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Asynchronous Write Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . 21
Table 6. Synchronous Read Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . . 21
Table 7. Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Device ID Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
www.DataTSahbeleet41U3.c.om Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Asynchronous Page Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Asynchronous Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Clock related AC timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21. Synchronous Burst Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 22. Synchronous Burst Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23. Power-Up and Deep Power-Down AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5/64
5 Page 
M69KB128AB
Signal descriptions
2.8 Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a write or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E remains Low.
2.9 Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system
bus frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
www.DataSheet4U.com The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations.
Latency counts are defined from the first Clock rising edge after L falling edge to the first
data input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.10
Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.11
Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the
Latch Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising
edge.
2.12
Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may
cause data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate
that the M69KB128AB device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched
while an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous
Read Operation in Variable Latency mode).
Typically, the WAIT pin of the M69KB128AB can be connected to a shared WAIT signal used
by the processor to coordinate transactions with multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
11/64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M69KB128AB.PDF ] | |
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