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ARM966E-S PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ARM966E-S
기능 Microprocessor Core
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ARM966E-S 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Technical
Manual
ARM966E-S
Microprocessor Core
June 2001
Preliminary
®




ARM966E-S pdf, 반도체, 판매, 대치품
Chapter 6, Write Buffer, describes the internal Write Buffer.
Chapter 7, System Controller, describes the internwawl w.DataSheet4U.com
Coprocessor 15 block, which the CPU uses to control the Write
Buffer and Instruction and Data RAMs.
Chapter 8, Tightly Coupled RAM, describes the two built-in RAMs:
the Instruction RAM and the Data RAM.
Chapter 9, External Coprocessor Interface, describes the external
coprocessor interface through which additional on-chip coprocessors
connect.
Chapter 10, Debug, describes the operation of the ARM966E-S
debug interface, which is based on the IEEE Std. 1149.1-1990.
Chapter 11, Test Methodology, discusses the available test
methods.
Appendix A, ARM9E-S Enhanced Instructions, describes the
enhancements to the ARM9E-S instruction set.
Related Publications
ARM946E-S Microprocessor Core with Cache Technical Manual,
Document No. DB14-000104-00
Standard Test Access Port and Boundary Scan Architecture,
IEEE Standard 1149.1-1990
ARM940T Datasheet, ARM Ltd., Document No. ARM DDI 0092A-04
ARM9 Architecture Reference Manual, ARM Ltd., Document No.
ARM DDI 0100
ARM9E-S Technical Reference Manual, ARM Ltd., Document No.
ARM DDI 0165
ARM Hurricane Engineering Specification
AHB Specification (Rev. 2.0), ARM Ltd., Document No. ARM IHI 0011
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
iv Preface
Rev. A
Copyright © 1999–2001 by LSI Logic Corporation. All rights reserved.

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ARM966E-S 전자부품, 판매, 대치품
Contents
www.DataSheet4U.com
Chapter 1
Chapter 2
Introduction
1.1 Overview
1.2 Block Diagram Description
1.2.1 ARM9E-S Processor Core
1.2.2 System Controller
1.2.3 CP15 System Control Coprocessor
1.2.4 Address Decoders
1.2.5 Instruction and Data RAMs
1.2.6 DMA Interface
1.2.7 AHB Interface Unit and Write Buffer
1.2.8 External Coprocessor Interface
1.2.9 JTAG and Debug Port
1.2.10 Embedded Trace Module Interface
1.3 Feature Summary
1.4 CoreWare Program
Signal Descriptions
2.1 AHB Interface
2.2 Coprocessor Interface
2.3 Instruction RAM Signals
2.4 Data RAM Signals
2.5 DMA Signals
2.6 Debug Signals
2.7 ETM Interface Signals
2.8 Miscellaneous Signals
2.9 Initialization Control Signals
2.10 ATPG Scan Control Signals
1-1
1-2
1-3
1-4
1-4
1-4
1-4
1-5
1-5
1-5
1-5
1-6
1-6
1-6
2-3
2-8
2-10
2-10
2-12
2-14
2-16
2-20
2-21
2-21
ARM966E-S Microprocessor Core
Rev. A
Copyright © 1999–2001 by LSI Logic Corporation. All rights reserved.
vii

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ARM966E-S

Microprocessor Core

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