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PDF ARM966E-S Data sheet ( Hoja de datos )
| Número de pieza | ARM966E-S | |
| Descripción | Microprocessor Core | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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Technical
Manual
ARM966E-S
Microprocessor Core
June 2001
Preliminary
®
1 page  
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
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Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Preface
Rev. A
Copyright © 1999–2001 by LSI Logic Corporation. All rights reserved.
v
5 Page 
Appendix A
Figures
11.2 RAMBIST
ARM9E-S Enhanced Instructions
Index
Customer Feedback
11-1
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1.1 ARM966E-S Block Diagram
2.1 ARM966E-S Signal Diagram
3.1 Coprocessor Instruction Format
3.2 ARM966E-S Memory Map
3.3 CPU Register Organization
3.4 Program Status Registers (CPSR and SPSR) Format
5.1 Multiplexer Interconnection
5.2 Transfer Type Examples
5.3 AHB Clock Relationships
5.4 Simple Transfer
5.5 Transfer with Wait States
5.6 Multiple Transfers
5.7 Incrementing Bursts with Undefined Lengths
5.8 Transfer with Retry Response
5.9 Error Response
8.1 SRAM Read Cycle
8.2 ARM966E-S SRAM Hierarchy
8.3 ONESEGX32 Interface
8.4 FOURSEGX32 Interface
8.5 FOURSEGX8 Interface
9.1 CLK and CPCLKEN Timing
9.2 LDC/STC Cycle Timing
9.3 MCR/MRC Cycle Timing
9.4 Interlocked MCR
9.5 Late Cancelled CDP
9.6 Privileged Instructions
9.7 Stalling and Interrupts
1-3
2-2
3-4
3-5
3-6
3-8
5-2
5-4
5-11
5-13
5-14
5-14
5-16
5-18
5-18
8-2
8-6
8-7
8-8
8-10
9-2
9-3
9-6
9-7
9-8
9-9
9-10
Contents
Rev. A
Copyright © 1999–2001 by LSI Logic Corporation. All rights reserved.
xi
11 Page | ||
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| PDF Descargar | [ Datasheet ARM966E-S.PDF ] | |
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