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K7P321874C 데이터시트 PDF




Samsung Electronics에서 제조한 전자 부품 K7P321874C은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 K7P321874C 기능
기능 1Mx36 & 2Mx18 SRAM
제조업체 Samsung Electronics
로고 Samsung Electronics 로고


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K7P321874C 데이터시트, 핀배열, 회로
K7P323674C
K7P321874C
Preliminary
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
32Mb C-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Jan. 2005
Rev 0.1




K7P321874C pdf, 반도체, 판매, 대치품
K7P323674C
K7P321874C
FUNCTIONAL BLOCK DIAGRAM
SA[0:19] or SA[0:20]
CK
SS
SW
SWx
(x=a, b, c, d)
or (x=a, b)
Latch
Latch
SW
Register
SWx
Register
SS
Register
G
ZZ
K CK
K
Read
Address
Register
SW
Register
SWx
Register
SS
Register
Preliminary
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
Write
Address
Register
1
0
1Mx36
or
2Mx18
Array
Column Decoder
Write/Read Circuit
01
Data In
Register
Data Out
Register
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
VDD
VDDQ
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Output Power Supply
Pin Name
VREF
M1, M2
G
SS
TCK
TMS
TDI
TDO
ZQ
VSS
NC
Pin Description
HSTL Input Reference Voltage
Read Protocol Mode Pins ( M1=VSS, M2=VDDQ )
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Output Driver Impedance Control
GND
No Connection
-4-
Jan. 2005
Rev 0.1

4페이지










K7P321874C 전자부품, 판매, 대치품
K7P323674C
K7P321874C
Preliminary
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
TRUTH TABLE
K ZZ G SS SW
XHXXX
X L HXX
L LHX
L L LH
LXLL
LXLL
LXLL
LXLL
LXLL
LXLL
NOTE : K & K are complementary
SWa
X
X
X
X
H
L
H
H
H
L
SWb
X
X
X
X
H
H
L
H
H
L
SWc
X
X
X
X
H
H
H
L
H
L
SWd
X
X
X
X
H
H
H
H
L
L
DQa
Hi-Z
Hi-Z
Hi-Z
DOUT
Hi-Z
DIN
Hi-Z
Hi-Z
Hi-Z
DIN
DQb
Hi-Z
Hi-Z
Hi-Z
DOUT
Hi-Z
Hi-Z
DIN
Hi-Z
Hi-Z
DIN
DQc
Hi-Z
Hi-Z
Hi-Z
DOUT
Hi-Z
Hi-Z
Hi-Z
DIN
Hi-Z
DIN
DQd
Operation
Hi-Z Power Down Mode. No Operation
Hi-Z Output Disabled.
Hi-Z Output Disabled. No Operation
DOUT Read Cycle
Hi-Z No Bytes Written
Hi-Z Write first byte
Hi-Z Write second byte
Hi-Z Write third byte
DIN Write fourth byte
DIN Write all bytes
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
Voltage on any I/O pin Relative to VSS
VDDQ
VIN
-0.5 to 2.4
-0.5 to VDDQ+0.5 (2.4V MAX)
V
V
Output Short-Circuit Current
IOUT
25 mA
Operating Temperature
Storage Temperature
TOPR
TSTG
0 to 70
-55 to 125
°C
°C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Input Low Level
Input Reference Voltage
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
Symbol
VDD1
VDD2
VDDQ
VIH
VIL
VREF
VIN-CLK
VDIF-
VCM-
Min
2.37
1.7
1.4
VREF+0.1
-0.3
0.6
-0.3
0.1
0.6
Typ
2.5
1.8
1.5
-
-
VDDQ/2
-
-
0.75
Max
2.63
1.9
1.9
VDDQ+0.3
VREF-0.1
0.9
VDDQ+0.3
VDDQ+0.6
0.9
Unit
V
V
V
V
V
V
V
V
V
Note
7
7
1, 2
1, 3
1, 4
1, 5
1, 6
NOTE : 1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parame-
ters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width 3ns).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width 3ns).
4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.
5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.
6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock
7. This device support both 250MHz and 300MHz frequency at VDD1. and support only 250MHz frequency at VDD2.
-7-
Jan. 2005
Rev 0.1

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관련 데이터시트

부품번호상세설명 및 기능제조사
K7P321874C

1Mx36 & 2Mx18 SRAM

Samsung Electronics
Samsung Electronics
K7P321874C

1Mx36 & 2Mx18 SRAM

Samsung Electronics
Samsung Electronics

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