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PDF ADP3207 Data sheet ( Hoja de datos )
| Número de pieza | ADP3207 | |
| Descripción | 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller | |
| Fabricantes | ANALOG DEVICES | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3207 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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7-Bit Programmable Multiphase Mobile
CPU Synchronous Buck Controllerwww.DataSheet4U.com
ADP3207
FEATURES
1-, 2-, or 3-phase operation at up to 750 kHz per phase
±8 mV worst-case differential sensing error over
temperature
Interleaved PWM outputs for driving external high power
MOSFET drivers
Automatic power-saving modes maximize efficiency during
light load and deeper sleep operation
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for
additional design flexibility
Built-in power-good masking supports VID on-the-fly
7-bit digitally programmable 0.3 V to 1.5 V output
Overload and short-circuit protection with programmable
latch-off delay
Built-in clock enable output delays CPU clock until CPU
supply voltage stabilizes
APPLICATIONS
Notebook power supplies for next generation Intel®
processors
GENERAL DESCRIPTION
The ADP32071 is a high efficiency, multiphase, synchronous,
buck-switching regulator controller optimized for converting
notebook battery voltage into the core supply voltage required
by high performance Intel processors. The part uses an internal
7-bit DAC to read voltage identification (VID) code directly
from the processor that sets the output voltage. The phase
relationship of the output signals can be programmed to
provide 1-, 2-, or 3-phase operation, allowing for the
construction of up to three interleaved buck-switching stages.
The ADP3207 uses a multimode architecture to drive the logic-
level PWM outputs at a programmable switching frequency that
can be optimized depending on the output current requirement.
The part switches between multiphase and single-phase operation
to maximize its effectiveness under all load conditions. In addition,
the ADP3207 includes a programmable slope function to adjust
the output voltage as a function of the load current. As a result,
it is always best positioned for a system transient.
1 Patent 6,683,441.
FUNCTIONAL BLOCK DIAGRAM
EN 1
GND 20
TTSENSE 30
VRTT 29
VCC VRPM RRPM RT RAMPADJ
31 12
UVLO
SHUTDOWN
AND BIAS
THERMAL
THROTTLING
CONTROL
13 14
15
OSCILLATOR
CURRENT
BALANCING
CIRCUIT
ADP3207
SET EN
+
C–MP
RESET
1/2/3 – PHASE
DRIVER
+
C–MP
LOGIC
RESET
26 PWM1
25 PWM2
1.7V
CSREF
+
C–MP
RESET
CROWBAR
24 PWM3
DAC + 200mV
CSREF
DAC – 300mV
PGDELAY 3
+
–
PWRGD 2
DELAY
ILIMIT 11
CURRENT LIMIT
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
19 CSCOMP
18 CSSUM
17 CSREF
CLKEN 4
COMP 7
SOFT
START
6 FB
+ 16 LLSET
– 33 DPRSTP
SOFT START/
BOOT/
DEEPER
SLEEP
CONTROL
32 PSI
10 DPRSLP
9 STSET
28 DCM
PRECISION
REFERENCE
VID
DAC
27 OD
8 SS
5 34 35 36 37 38 39 40
Figure 1.
The chip also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
The ADP3207 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 40-lead
LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
POWER-GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Output Leakage Current
Power-Good Delay Timer
PGDELAY Threshold
PGDELAY Charge Current
PGDELAY Discharge Resistance
Power-Good Masking Time
Crowbar Threshold Voltage
Reverse Voltage Detection
Threshold
CLKEN OUTPUT
Output Low Voltage
Output Leakage Current
OD/DCM OUTPUTS
Output Low Voltage
Output High Voltage
PWM OUTPUTS
Output Low Voltage
Output High Voltage
SUPPLY
Supply Voltage Range
Supply Current
VCCOK Threshold Voltage
VCC UVLO Threshold Voltage
VCC Hysteresis2
Symbol
VCSREF(UV)
VCSREF(OV)
VPWRGD(L)
IPWRGD
VPGDELAY(TH)
IPGDELAY
RPGDELAY
VCSREF(CB)
VCSREF(RV)
VOL
VOH
VOL(PWM)
VOH(PWM)
VCC
VCCOK
VCCUVLO
Conditions
Relative to nominal DAC voltage
Relative to nominal DAC voltage
IPWRGD(SINK) = 4 mA
VPWRDG = 5 V
VPGDELAY = 2.0 V
VPGDELAY = 0.2 V
Relative to FBRTN
Relative to FBRTN
CSREF is falling
CSREF is rising
I CLKEN(SINK) = 4 mA
V CLKEN = 5 V, VSS = GND
ISINK = 400 µA
ISOURCE = 400 µA
IPWM(SINK) = 400 µA
IPWM(SOURCE) = 400 µA
Normal mode
EN = 0 V
VCC is rising
VCC is falling
1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2 Guaranteed by design or bench characterization, not production tested.
ADP3207
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Min Typ Max Units
−240
150
−300
200
85
−360
250
250
3
mV
mV
mV
μA
2.9
1.9
550
130
1.65 1.7
V
µA
Ω
μs
1.75 V
−300 −350 mV
−75 −10 mV
30 400 mV
3 µA
10 500 mV
45
V
10
4.0 5
500 mV
V
4.5 5.5 V
4.2 10 mA
190 300 µA
4.4 4.5 V
4.0 4.15
V
260 mV
Rev. 0 | Page 5 of 32
5 Page 
THEORY OF OPERATION
The ADP3207 combines a multimode PWM/RPM (ramp pulse
modulated) control with multiphase logic outputs for use in 1-,
2-, and 3-phase synchronous buck CPU core supply power
converters. The internal 7-bit VID DAC conforms to Intel
IMVP-6 specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling high currents in a single-
phase converter puts high thermal stress on the system
components such as the inductors and MOSFETs.
The multimode control of the ADP3207 ensures a stable high
performance topology for:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and minimal output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
• Tight load line regulation and accuracy
• High current output by supporting up to 3-phase operation
• Reduced output ripple due to multiphase ripple cancellation
• High power conversion efficiency both at heavy load and
light load
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation by allowing optimization of design
for low cost or high performance
NUMBER OF PHASES
The number of operational phases and their phase relationship
is determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3207 operates as a 3-phase
controller. For 2-phase operation, the PWM3 pin is connected
to VCC 5 V programs, and for 1-phase operation, the PWM3
and PWM2 pins are connected to VCC 5 V programs.
When the ADP3207 is initially enabled, the controller sinks 50 µA
on the PWM2 and PWM3 pins. An internal comparator checks
the voltage of each pin against a high threshold of 3 V. If the pin
voltage is high due to pull up to the VCC 5 V rail, then the
phase is disabled. The phase detection is made during the first
three clock cycles of the internal oscillator. After phase detection,
the 50 µA current sink is removed. The pins that are not connected
to the VCC 5 V rail function as normal PWM outputs. The pins
that are connected to VCC enter into high impedance state.
ADP3207
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The PWM outputs are 5 V logic-level signals intended for
driving external gate drivers such as the ADP3419. Because
each phase is monitored independently, operation approaching
100% duty cycle is possible. In addition, more than one output
can operate at a time to allow overlapping phases.
OPERATION MODES
For ADP3207, the number of phases can be selected by the user
as described in the Number of Phases section, or they can
dynamically change based on system signals to optimize the
power conversion efficiency at heavy and light CPU loads.
During a VID transient or at a heavy load condition, indicated
by DPRSLP going low and PSI going high, the ADP3207 runs
in full-phase mode. All user selected phases operate in inter-
leaved PWM mode that results in minimal VCORE ripple
and best transient performance. While in light load mode,
indicated by either PSI going low or DPRSLP going high,
only Phase 1 of ADP3207 is in operation to maximize
power conversion efficiency.
In addition to the change of phase number, the ADP3207
dynamically changes operation modes. In multiphase operation,
the ADP3207 runs in PWM mode, with switching frequency
controlled by the master clock. In single-phase mode based on
PSI signal, the ADP3207 switches to RPM mode, where the
switching frequency is no longer controlled by the master clock,
but by the ripple voltage appearing on the COMP pin. The
PWM1 pin is set to high each time the COMP pin voltage rises
to a limit determined by the VID voltage and programmed
by the external resistor connected between Pin VRPM and
Pin RRPM. In single-phase mode based on the DPRSLP signal,
the ADP3207 runs in RPM mode, with the synchronous
rectifier (low-side) MOSFETs of Phase 1 being controlled by the
DCM pin to prevent any reverse inductor current. Thus, the
switch frequency varies with the load current, resulting in
maximum power conversion efficiency in deeper sleep mode of
CPU operation. In addition, during any VID transient, system
transient (entry/exit of deeper sleep), or current limit, the
ADP3207 goes into full phase mode, regardless of DPRSLP and
PSI signals, eliminating current stress to Phase 1.
Table 4 summarizes how the ADP3207 dynamically changes
phase number and operation modes based on system signals
and operating conditions.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3207.PDF ] | |
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