|
|
PDF GTL2009 Data sheet ( Hoja de datos )
| Número de pieza | GTL2009 | |
| Descripción | 3-bit GTL Front-Side Bus frequency comparator | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de GTL2009 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
Rev. 01 — 22 September 2005
Product data sheet
1. General description
The GTL2009 is designed for the Nocona and Dempsey/Blackford dual Intel Xeon
processor platforms to compare the Front-Side Bus (FSB) frequency settings and set the
common FSB frequency at the lowest setting if both processor slots are occupied or the
FSB setting of the occupied processor slot if only one processor is being used. A default
FSB frequency of 100 MHz is initially set upon power-up when VDD is greater than 1.5 V.
Magnitude comparisons and frequency multiplexing to compute the common FSB
frequency occurs when the two 3-bit FSB GTL inputs from the chip sets are valid. The
common FSB frequency GTL outputs switch from the default frequency to the computed
frequency when the GTL reference voltage input (VREF) crosses a static 0.6 V internally
generated input comparator reference voltage. The GTL2009 then continually monitors
the FSB frequency and slot occupied inputs for any further changes.
The Nocona and Dempsey/Blackford Xeon processors specify a VTT of 1.2 V and 1.1 V,
as well as a nominal Vref of 0.76 V and 0.73 V respectively. To allow for future voltage level
changes that may extend Vref to 0.63 of VTT (minimum of 0.693 V with VTT of 1.1 V) the
GTL2009 allows a minimum Vref of 0.66 V. Characterization results show that there is little
DC or AC performance variation between these levels.
The GTL2009 is a companion chip to the GTL2006 platform health management
GTL-to-LVTTL translator and the newer GTL2007 that adds an enable function that
disables the error output to the monitoring agent for platforms that monitor the individual
error conditions from each processor.
2. Features
s Compares FSB frequency inputs to set the lowest frequency as the common bus
frequency.
s Operates at a range of GTL signal levels
s 3.0 V to 3.6 V operation
s LVTTL I/O are not 5 V tolerant
s Companion chip to GTL2006 and GTL2007
s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
s Latch-up testing is done to JEDEC Standard JESD78, which exceeds 500 mA
s Available in TSSOP16 package
1 page  
Philips Semiconductors
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
7.2 Default conditions input
The FSB GTL output data is masked and a specific default value (100 MHz) is inserted
upon power-up when VDD is greater than 1.5 V. The FSB GTL output data is unmasked
and valid data is supplied when the VREF input crosses a static 0.6 V internally generated
input comparator reference voltage. For slowly rising GTL VTT supply (0.7 V/500 µs), the
switch-over happens at the 0.6 V threshold. For fast rising GTL VTT supply (0.7 V/100 ns),
the switch-over typically occurs between 350 ns to 1.5 µs after the 0.6 V threshold is
exceeded.
The AO1 and AO2 outputs do not have ‘default conditions’ like those assigned to the GTL
outputs. Instead, these two pins will power-up according to the conditions applied to the
1A1 and 2A1 input pins as shown in Table 8. If the slot is occupied, the input is LOW.
Table 8: AO1 and AO2 power-up conditions
H = HIGH; L = LOW.
1AI 2AI VDD
L L <1.5 V
L L >1.5 V
L H <1.5 V
L H >1.5 V
HL
<1.5 V
HL
>1.5 V
H H <1.5 V
H H >1.5 V
AO1
L
H
L
L
L
L
L
H
AO2
L
H
L
L
L
H
L
H
It is important to note that the AO1 and AO2 outputs may be valid a little before 1.5 V and
will rise with VDD. Valid outputs from the system level perspective will be achieved after
VDD is in regulation, VTT ramps up, and after the internal propagation delay of the
GTL2009. No firm answer for this can be given since the time it takes for VDD to be in
regulation varies from 100 ms to 1000 ms, and the rise time of VTT is unknown. The
GTL2009 outputs are valid after the GTL inputs are valid plus 19.6 ns (worst-case
propagation delay of the GTL-to-LVTTL path).
9397 750 13556
Product data sheet
Rev. 01 — 22 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 17
5 Page 
Philips Semiconductors
13. Test information
GTL2009
www.DataSheet4U.com
3-bit GTL Front-Side Bus frequency comparator
PULSE
GENERATOR
VI
VDD
D.U.T.
VO
RT
CL
50 pF
RL
500 Ω
Fig 10. Load circuitry for A outputs
002aab006
PULSE
GENERATOR
VTT
VDD
50 Ω
VI VO
D.U.T.
RT
CL
30 pF
002aab007
Fig 11. Load circuit for B outputs
Definitions:
RL — load resistor
CL — load capacitance includes jig and probe capacitance.
RT — termination resistance should be equal to Zo of pulse generators.
9397 750 13556
Product data sheet
Rev. 01 — 22 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet GTL2009.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| GTL2000 | 22-bit GTL processor voltage clamp | NXP Semiconductors |
| GTL2000DL | 22-bit GTL processor voltage clamp | NXP Semiconductors |
| GTL2002 | 2-bit bi-directional low voltage translator | NXP Semiconductors |
| GTL2002D | 2-bit bi-directional low voltage translator | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |