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AD9941 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9941은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD9941 기능
기능 56 MSPS Imaging Signal Processor
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AD9941 데이터시트, 핀배열, 회로
FEATURES
Differential sensor input with 1 V p-p input range
0 dB/6 dB variable gain amplifier (VGA)
Low noise optical black clamp circuit
14-bit, 56 MSPS analog-to-digital converter (ADC)
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
Low power CMOS: 145 mW @ 3.0 V, 56 MHz
48-lead LQFP package
APPLICATIONS
Digital still cameras using CMOS imagers
Professional HDTV camcorders
Professional/high-end digital cameras
Broadcast cameras
Complete 14-Bit, 56 MSPS
Imaging Signal Processorwww.DataSheet4U.com
AD9941
GENERAL DESCRIPTION
The AD9941 is a complete analog signal processor for imaging
applications that do not require correlated double sampling
(CDS). It is also suitable for processing the output signal from
the AD9940 CDS front end product. It features a 56 MHz, single-
channel architecture designed to sample and condition the output
of CMOS imagers and CCD arrays already containing on-chip
CDS. The AD9941 signal chain consists of a differential input
sample-and-hold amplifier (SHA), a digitally controlled variable
gain amplifier (VGA), a black level clamp, and a 14-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface.
The AD9941 operates from a single 3 V supply, typically
dissipates 145 mW, and is packaged in a 48-lead LQFP.
VIN+
VIN–
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
REFT REFB
PBLK
AD9941
SHA
0dB, 6dB
VGA
BAND GAP
REFERENCE
14-BIT
ADC
CLP
14
INTERNAL
REGISTERS
8
DIGITAL
INTERFACE
BLK CLAMP
LEVEL
SL SCK SDATA
Figure 1.
ADCLK
DRVDD
DRVSS
DOUT
CLPOB
DVDD
DVSS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.




AD9941 pdf, 반도체, 판매, 대치품
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD, fADCLK = 56 MHz, unless otherwise noted.
Table 3.
Parameter
ANALOG INPUTS (VIN+, VIN−)
Input Common-Mode Range1
Maximum Input Amplitude1
Maximum Differential Input Amplitude1
OB Correction Range
Gain 1 (6 dB)1
Gain 2 (0 dB)1
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Range
CCD Mode Gain 1
CCD Mode Gain 2
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 255)
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
Min
1.1
1.0
2.0
5.0
−0.5
14
Typ Max
2.3
±90
±180
5.5
0
256
0
1020
2
6.0
+0.5
±0.5
Guaranteed
0.3
2.0
2.0
1.0
1 Input signal characteristics defined as
VIN–
BLACK
LEVEL
VIN+
GND
MAX OB OFFSET
WHITE
LEVEL
2.3V
1V p-p MAX INPUT SIGNAL SWING, VIN+ AND VIN–
2V p-p MAX DIFFERENTIAL SIGNAL, VIN+ – VIN–
1.1V
Unit
V
V p-p
V p-p
mV
mV
Steps
dB
dB
Steps
LSB
LSB
Bits
LSB
% FS
V p-p
V
V
AD9941
www.DataSheet4U.com
Notes
Linear operating range for VIN+, VIN−
VIN+ and VIN− signal swing
Defined as VIN+ − VIN−
OB offset shown in Note 1
Clamp level = 4 × REFBLK
Rev. 0 | Page 4 of 16

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AD9941 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9941
www.DataSheet4U.com
48 47 46 45 44 43 42 41 40 39 38 37
D2 1
D3 2
D4 3
D5 4
D6 5
D7 6
D8 7
D9 8
D10 9
D11 10
D12 11
D13 12
PIN 1
AD9941
TOP VIEW
(Not to Scale)
36 NC
35 AVSS
34 NC
33 AVDD
32 NC
31 VIN–
30 VIN+
29 NC
28 NC
27 NC
26 NC
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1 to 12
D2 to D13
13 DRVDD
14 DRVSS
15 DVSS
16 ADCLK
17 DVDD
18, 21 to 29, 32, NC
34, 36, 40, 41
19 PBLK
20 CLPOB
30 VIN+
31 VIN−
33 AVDD
35 AVSS
37 DVSS
38 REFT
39 REFB
42 DVSS
43 RST
44 SDATA
45 SCK
46 SL
47 D0
48 D1
Type
DO
P
P
P
DI
P
NC
DI
DI
AI
AI
P
P
P
AO
AO
P
DI
DI
DI
DI
DO
DO
Description
Digital Data Outputs
Digital Output Driver Supply
Digital Output Ground
Digital Ground
Digital Data Output Clock
Digital Supply
No Connection (tie to VDD or GND)
Preblanking Clock Input (internal 50 kΩ pull-up)
Black Level Clamp Clock Input
Positive Data Input
Negative Data Input
Analog Supply
Analog Ground (GND)
Digital Ground
ADC Reference Voltage Top (bypass to GND with a 0.1 μF capacitor)
ADC Reference Voltage Bottom (bypass to GND with a 0.1 μF capacitor)
Digital Ground
Reset Control for Internal Registers (active low)
Serial Data Input Signal
Serial Clock
Serial Load Enable
Digital Data Output
Digital Data Output
Rev. 0 | Page 7 of 16

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