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PDF CS5374 Data sheet ( Hoja de datos )
| Número de pieza | CS5374 | |
| Descripción | Dual High-performance Amplifier | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5374
www.DataSheet4U.com
Dual High-performance Amplifier & ΔΣ Modulator
Features
High Input Impedance Differential Amplifier
• Ultra-low input bias: < 1 pA
• Max signal amplitude: 5 Vpp differential
Fourth Order Delta-Sigma (ΔΣ) Modulator
• Signal Bandwidth: DC to 2 kHz
• Common mode rejection: 110 dB CMRR
Differential Analog Input, Digital ΔΣ Output
• Multiplexed inputs: INA, INB, 800Ω termination
• Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x
Excellent Amplifier Noise Performance
• 1.5 μVpp between 0.1 Hz and 10 Hz
• 11 nV / √Hz from 200 Hz to 2 kHz
High Modulator Dynamic Range
• 126 dB SNR @ 215 Hz BW (2 ms sampling)
• 123 dB SNR @ 430 Hz BW (1 ms sampling)
Low Total Harmonic Distortion
• –118 dB THD typical (0.000126%)
• –108 dB THD maximum (0.0004%)
Low Power Consumption
• Normal operation: 6.5 mA per channel
• Power down: 15 μA per channel max
Dual Power Supply Configuration
• VA+ = +2.5 V; VA– = –2.5 V; VD = +3.3 V
Description
The CS5374 combines two marine seismic analog mea-
surement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a high
input impedance programmable gain differential amplifi-
er that buffers analog signals into a high-performance,
fourth-order ΔΣ modulator. The low-noise ΔΣ modulator
converts the analog signal into a one-bit serial bit stream
suitable for the CS5376A digital filter.
Each amplifier has two sets of external inputs, INA and
INB, to simplify system design as inputs from a hydro-
phone sensor or the CS4373A test DAC. An internal
800Ω termination can also be selected for noise tests.
Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x,
32x, 64x) and match the CS4373A test DAC output at-
tenuation settings for full-scale testing at all gain ranges.
Both the input multiplexer and gain are set by registers
accessed through a standard SPI™ port.
Each fourth-order ΔΣ modulator has very high dynamic
range combined with low total harmonic distortion and
low power consumption. It converts differential analog
signals from the amplifier to an oversampled ΔΣ serial bit
stream which is decimated by the CS5376A digital filter
to a 24-bit output at the final output word rate.
ORDERING INFORMATION
See page 43.
INA1+
INB1+
GUARD1
+
-
MUX1
INA1-
INB1-
VA+
VA-
INA2+
INB2+
-
+
+
-
OUT1+ OUT1- INR1- INF1- INF1+INR1+
VA- VA+
Reset, Clock,
and
Synchronization
RST
MCLK
MSYNC
CS5374
4th Order
Modulator
4th Order
Modulator
MDATA1
MFLAG1
VD
GND
MDATA2
MFLAG2
MUX2
INA2-
INB2-
GUARD2
-
+
SPITM Serial
Interface
SDO
SDI
SCLK
CS
OUT2+ OUT2- INR2- INF2- INF2+INR2+
VREF+ VREF-
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
OCT '09
DS862F1
1 page  
CS5374
DS862F1
CS5374
THERMAL CHARACTERISTICS
www.DataSheet4
Parameter
Symbol Min Typ Max
Unit
Ambient Operating Temperature
TA
-10 -
70
°C
Storage Temperature Range
TSTR
-65
-
150
°C
Allowable Junction Temperature
TJCT
-
- 125
°C
Junction to Ambient Thermal Impedance (4-layer PCB)
θJA
- 26 - °C / W
ANALOG CHARACTERISTICS
Parameter
Amplifier Inputs
Signal Frequencies
Differential Gain
Common Mode Gain
Common Mode Voltage
Voltage Range (Signal + Vcm)
Full Scale Differential Input
Differential Input Impedance
Common Mode Input Impedance
Input Bias Current
Amplifier Outputs
Full Scale Output, Differential
Output Voltage Range (Signal + Vcm)
Output Impedance
Output Impedance Drift
Output Current
Load Capacitance
Guard Outputs
Guard Output Voltage
Guard Output Impedance
Guard Output Current
Guard Load Capacitance
Symbol
(Note 7)
x1
x2 - x64
x1
x2
x4
x8
x16
x32
x64
BW
GAIN
GAINCM
Vcm
VIN
VINFS
ZINDIFF
ZINCM
IIN
(Note 8)
(Note 8)
VOUT
VRNG
ZOUT
ZTC
IOUT
CL
(Note 8)
VGUARD
ZGOUT
IGOUT
CGL
Min Typ Max
DC
x1
-
-
(VA-)+0.7
(VA-)+0.7
-
-
-
-
-
-
-
-
-
-
- 2000
- x64
x1 -
(VA-)+2.5
-
- (VA+)-1.25
- (VA+)-1.75
-5
- 2.5
- 1.25
- 625
- 312.5
- 156.25
- 78.125
1, 20
-
0.5, 40
-
1 40
-
(VA-)+0.5
-
-
-
-
-
-
40
0.38
-
-
5
(VA+)-0.5
-
-
+25
100
- Vcm -
- 500 -
- - 40
- - 100
Unit
Hz
V
V
Vpp
Vpp
Vpp
mVpp
mVpp
mVpp
mVpp
TΩ, pF
TΩ, pF
pA
Vpp
V
Ω
Ω/°C
mA
nF
V
Ω
μA
pF
Notes: 7. Common mode signals pass through the differential amplifier architecture and are rejected by the
modulator CMRR.
8. Output impedance characteristics are approximate and can vary up to ±30% depending on process
parameters.
DS862F1
5
5 Page 
CS5374
DS862F1
CS5374
DIGITAL CHARACTERISTICS (CONT.)
Parameter
Symbol Min
Master Clock Input
MCLK Frequency
MCLK Duty Cycle
MCLK Rise Time
MCLK Fall Time
MCLK Jitter (in-band or aliased in-band)
MCLK Jitter (out-of-band)
Master Sync Input
MSYNC Setup Time to MCLK Falling
MSYNC Period
MSYNC Hold Time after MCLK Falling
MDATA Output
MDATA Output Bit Rate
MDATA Output One’s Density Range
Full-scale Output Code, Offset Corrected
(Note 23)
fMCLK
MCLKDTC
tRISE
tFALL
MCLKIBJ
MCLKOBJ
-
40
-
-
-
-
(Note 24)
(Note 24)
(Note 24)
tMSS
tMSYNC
tMSH
20
40
20
(Note 22)
(Note 25)
fMDATA
MDAT1D
MDATFS
-
14
0xA2E736
Typ
2.048
-
-
-
-
-
366
976
610
512
-
-
www.DataSheet4U.com
Max
Unit
- MHz
60 %
50 ns
50 ns
300 ps
1 ns
- ns
- ns
- ns
-
86
0x5D18CA
kbits/s
%
Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically
enters a power-down state. See Power Supply Characteristics for typical power-down timing.
24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,
synchronization instant (t0) is on the next MCLK rising edge.
25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.
MCLK
MSYNC
MDATA
MFLAG
tMSS
tMSH
t0
tMSYNC
1 / fMCLK
1 / fMDATA
Figure 7. MCLK / MSYNC Timing Detail
DS862F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5374.PDF ] | |
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