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K7B163635B 데이터시트 PDF




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부품번호 K7B163635B 기능
기능 512Kx36 & 1Mx18 Synchronous SRAM
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K7B163635B 데이터시트, 핀배열, 회로
K7B163635B
K7B161835B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
18Mb B-die Sync. SRAM Specification
100TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - July 2005
Rev 1.0




K7B163635B pdf, 반도체, 판매, 대치품
K7B163635B
K7B161835B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
512Kx36 & 1Mx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 2.5 or 3.3V +/- 5% Power Supply.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A (Lead and Lead free package)
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-75
8.5
7.5
3.5
Unit
ns
ns
ns
GENERAL DESCRIPTION
The K7B163635B and K7B161835B are 18,874,368-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 512K(1M) words of 36(18) bits and integrates
address and control registers, a 2-bit burst address counter and
added some new functions for high performance cache RAM
applications; GW, BW, LBO, ZZ. Write cycles are internally self-
timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the systems burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B163635B and K7B161835B are fabricated using SAM-
SUNGs high performance CMOS technology and is available
in a 100pin TQFP package. Multiple power and ground pins are
utilized to minimize ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS A0~A1
COUNTER
512Kx36, 1Mx18
MEMORY
ARRAY
ADSP
A0~A18
or A0~A19
A0~A1
ADDRESS
REGISTER
A2~A18
or A2~A19
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd DQPa,DQPb
CONTROL
LOGIC
OUTPUT
BUFFER
DATA-IN
REGISTER
- 4 - July 2005
Rev 1.0

4페이지










K7B163635B 전자부품, 판매, 대치품
K7B163635B
K7B161835B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
FUNCTION DESCRIPTION
The K7B163635B and K7B161835B are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B163635B, a 512Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
BQ TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Case 3
A1 A0
10
11
00
01
Case 3
A1 A0
10
11
00
01
(Interleaved Burst)
Case 4
A1 A0
11
10
01
00
(Linear Burst)
Case 4
A1 A0
11
00
01
10
- 7 - July 2005
Rev 1.0

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K7B163635B

512Kx36 & 1Mx18 Synchronous SRAM

Samsung Electronics
Samsung Electronics

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