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K7A161830B 데이터시트 PDF




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부품번호 K7A161830B 기능
기능 512Kx36 & 1Mx18 Synchronous SRAM
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K7A161830B 데이터시트, 핀배열, 회로
K7A163630B
K7A161830B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
18Mb B-die Sync. SRAM Specification
100TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - July 2005
Rev 1.0




K7A161830B pdf, 반도체, 판매, 대치품
K7A163630B
K7A161830B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 2.5 or 3.3V +/- 5% Power Supply.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A (Lead and Lead free package)
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol
Cycle Time
tCYC
Clock Access Time
tCD
Output Enable Access Time tOE
-25
4.0
2.6
2.6
-16 Unit
6.0 ns
3.5 ns
3.5 ns
GENERAL DESCRIPTION
The K7A163630B and K7A161830B are 18,874,368-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 512K(1M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor (ADSP) or address status cache controller
(ADSC) inputs. Subsequent burst addresses are generated
internally in the systems burst sequence and are con-
trolled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence
(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163630B and K7A161830B are fabricated using
SAMSUNGs high performance CMOS technology and is
available in a 100pin TQFP. Multiple power and ground
pins are utilized to minimize ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS A0~A1
COUNTER
512Kx36, 1Mx18
MEMORY
ARRAY
ADSP
A0~A18
or A0~A19
A0~A1
ADDRESS
REGISTER
A2~A18
or A2~A19
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd DQPa,DQPb
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
- 4 - July 2005
Rev 1.0

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K7A161830B 전자부품, 판매, 대치품
K7A163630B
K7A161830B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
FUNCTION DESCRIPTION
The K7A163630B and K7A161830B are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
BQ TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Case 3
A1 A0
10
11
00
01
Case 3
A1 A0
10
11
00
01
(Interleaved Burst)
Case 4
A1 A0
11
10
01
00
(Linear Burst)
Case 4
A1 A0
11
00
01
10
ASYNCHRONOUS TRUTH TABLE
Operation
Sleep Mode
Read
Write
Deselected
ZZ OE I/O STATUS
HX
High-Z
LL
DQ
L H High-Z
L X Din, High-Z
L X High-Z
Notes
1. X means "Dont Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
- 7 - July 2005
Rev 1.0

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512Kx36 & 1Mx18 Synchronous SRAM

SAMSUNG ELECTRONICS
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