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PDF PM7354 Data sheet ( Hoja de datos )
| Número de pieza | PM7354 | |
| Descripción | ATM to Ethernet Interworking at GE Wire Speed | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PM7354 (archivo pdf) en la parte inferior de esta página. Total 2 Páginas | ||
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PM7354
S/UNI Duplex GE
Preview
Monolithic IC for ATM to Ethernet Interworking at GE Wire Speed www.DataSheet4U.com
FEATURES
• The S/UNI DUPLEX GE is a monolithic
integrated circuit supporting wire speed
ATM to Ethernet inter-working at GE
rates. It provides the AAL5 SARing,
queuing/buffering, traffic management,
address translation, and multicast
functions necessary for interfacing an
ATM Utopia Level 2/POS-PHY Level 2
interface to 10/100/1000 Ethernet
interfaces.
• The extended (up to 144 ports) Utopia
Level 2 bus is designed to
accommodate the higher line densities
typical of ADSL DSLAMs. The dual
Ethernet integrated SERDES
accommodates backplane applications
where a 1:1 redundant Ethernet
interface is required. A separate parallel
Ethernet port creates the high
performance local interface needed for
packet add/drop applications such as
IGMP snooping.
APPLICATIONS
• Ethernet DSLAM: ADSL/VDSL line
cards and WAN uplink card
• ATM DSLAM: FE or GE WAN uplink
• ATM multi-service switch: GE interface
cards
• Router: ATM line cards
• Wireless base station: ATM to Ethernet
interworking.
BLOCK DIAGRAM
INTERFACES
• Dual fully integrated, 1.25Gbit/s, 8B10B
encoded 4-wire LVDS SERDES
interface for connecting the internal GE
MACs directly to a high-speed,
redundant serial back-plane or external
PHY.
• An additional (R)GMII / (R)MII parallel
Ethernet interface, which can also be
configured as two RMII interfaces.
• One 52 MHz, 16 bit Utopia Level 2
interface (Tx and Rx), extended to
support up to 144 PHYs as per ATM
Forum Utopia Level 2 specification af-
phy-0039.000, Appendix 1. This
interface is also configurable as a
SATURN compliant 52-MHz, 16-bit
POS-PHY Level 2 interface (Tx and Rx)
• One asynchronous 16 bit CPU interface
for device configuration and
alarm/status monitoring.
• One 32-bit SDRAM interface supporting
up to 2 Gbits of packet buffering.
Configurable as either DDR-I or DDR-
II.
ETHERNET TO ATM PROCESSING
• Receives Ethernet frames from both
SERDES interfaces and the parallel
interface simultaneously. Uses frame
filtering to drop redundant traffic
received on the protection SERDES
interface.
• Uses VLAN tag (802.1q VLAN address
+ 802.1p QoS bits) to identify traffic as
unicast or multicast, and to identify
destination port and class.
• SERDES to UL2/PL2, parallel Ethernet
to UL2/PL2, SERDES to parallel
Ethernet and parallel Ethernet to
SERDES switching are all supported.
• For traffic directed to the UL2/PL2
interface, performs RFC2684
compliant AAL5 segmentation for
origination of up to 576 ATM AAL5
VCs. Ethernet to ATM VCI/VPI
mapping provided via a software
configurable internal lookup table.
• Performs IP/Ethernet packet level
multicast using wire-speed packet
replication. Unicast and multicast
traffic is queued independently and is
merged onto the egress port via the
egress traffic scheduler. Head of line
blocking is avoided completely.
• Software configurable congestion
management policies implementing
Early Packet Discard & Partial Packet
Discard (EPD/PPD) or weighted
random early packet discard (WRED)
during periods of egress port
congestion.
GES
Ingress
Enet In MSTAT
Enet to AAL5 IWF
RAM Interface
DDR
Traffic Managment
RCTL
AAL5 to Enet IWF
Enet Out
GES
Egress
Enet In MSTAT
Enet to AAL5 IWF
QS600E
CSU
GEP
Ingress
Enet In MSTAT
Enet to AAL5 IWF
QMGR
QS600E
AAL5 to Enet IWF
AAL5 to Enet IWF
Enet Out
GEP
Egress
MPB
Ingress
ATM In
QS2M
Multicast
MSFF
MCAST
QS576A
ATM Out
MPB
Egress
PMC-2040392
Issue 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2005
All rights reserved.
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet PM7354.PDF ] | |
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