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43L0616A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 43L0616A
기능 A43L0616A
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43L0616A 데이터시트, 핀배열, 회로
A43L0616Awww.DataSheet4U.com
512K X 16 Bit X 2 Banks Synchronous DRAM
Document Title
512K X 16 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
History
Initial issue
Add input/output capacitance specification
Add Cl2 spec for (-5, -5.5, -6)
Modify MRS Set Cycle Waveform error
Add -U for industrial operating temperature range
Final spec. release
Some AC parameter unit update
Issue Date
December 4, 2000
February 13, 2001
Remark
Preliminary
April 11, 2001
May 29, 2001
Final
(May, 2001, Version 1.0)
AMIC Technology, Inc.




43L0616A pdf, 반도체, 판매, 대치품
A4w3wLw.0Da6ta1S6heAet4U.com
Pin Descriptions
Symbol
CLK
CS
CKE
A0~A10/AP
BA
Name
Description
System Clock
Active on the positive going edge to sample all inputs.
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Latches row addresses on the positive going edge of the CLK with RAS low.
Row Address Strobe
Enables row access & precharge.
CAS
Column Address
Strobe
WE Write Enable
L(U)DQM
Data Input/Output
Mask
DQ0-15
Data Input/Output
VDD/VSS
Power
Supply/Ground
VDDQ/VSSQ
Data Output
Power/Ground
NC/RFU
No Connection
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
(May, 2001, Version 1.0)
3 AMIC Technology, Inc.

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43L0616A 전자부품, 판매, 대치품
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C or -40ºC to +85ºC)
Parameter
AC input levels
Input timing measurement reference level
Input rise and all time (See note3)
Output timing measurement reference level
Output load condition
Value
VIH/VIL = 2.4V/0.4V
1.4V
tr/tf = 1ns/1ns
1.4V
See Fig.2
A4w3wLw.0Da6ta1S6heAet4U.com
Output
870
3.3V
1200
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
30pF
(Fig. 1) DC Output Load Circuit
OUTPUT
ZO=50
VTT =1.4V
50
30pF
(Fig. 2) AC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted)
Symbol
Parameter
CAS
Latency
-5
Min Max
-5.5
Min Max
-6
Min Max
-7
Unit Note
Min Max
tCC CLK cycle time
CLK to valid
tSAC
Output delay
tOH Output data hold time
tCH CLK high pulse width
3
2
3
2
3
2
5 5.5 6
7
1000
1000
1000
1000 ns
7788
- 4.5 - 5 - 5.5 -
- 5 - 5.5 - 6 -
6
ns
7
2 2 2.5 2.5 ns
2 2 2.5 2.5
- - - - ns
2 2 2.5 3
1
1,2
2
3
(May, 2001, Version 1.0)
6 AMIC Technology, Inc.

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