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PDF IP175ALF Data sheet ( Hoja de datos )
| Número de pieza | IP175ALF | |
| Descripción | 5 Port 10/100 Ethernet Integrated Switch | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP175ALF (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IP175A LF
Preliminary DawtawwS.DhaetaeStheet4U.com
5 Port 10/100 Ethernet Integrated Switch
Features
5 port 10/100 Ethernet switch with built in
transceivers and memory
Build in SSRAM for frame buffer
Built in storage of 1K MAC address
Support flow control
– Support IEEE802.3x for flow control for full
duplex mode operation
– Support backpressure for flow control for
half duplex mode operation
5 port switching fabric
– Support two-level hashing algorithm to
solve MAC address collision
– Support MAC address aging
– Store and forward mode
– Broadcast storm protection
– Full line speed capability of 148800 (14880)
packets/sec for 100M (10M)
– Support 1536 byte data transfer for VLAN
packet traffic
– Port base VLAN
– Port base CoS configuration
Integrate 5 ports transceiver
– Each port can be auto negotiable or forced
10M/100M, full/half duplex
– Each port can be configured as 100BaseFX
– Automatic MDI/MDI-X configuration
Support two MII, one SMI and extended MII
registers for router application
Built in regulator for 3.3v to 2.15v
LED status of Link, activity, Full/half duplex,
speed, and power on diagnostic function
Initial parameter setting by pin or EEPROM
(24LC01) configuration
Utilize single clock source (25Mhz)
0.25u technology
Support Lead Free package (Please refer to
the Order Information)
General Description
IP175A LF is a low cost 10/100 Ethernet single
chip switch. It integrates a 5-port switch controller,
SSRAM, and 5 10/100 Ethernet transceivers.
Each of the transceivers complies with the
IEEE802.3, IEEE802.3u, and IEEE802.3x
specifications. The transceivers are designed in
DSP approach with 0.25um technology; they have
high noise immunity and robust performance.
IP175A LF operates in store and forward mode. It
supports flow control, auto MDI/MDI-X, CoS, port
base VLAN, and LED functions, etc. Each port can
be configured to auto-negotiation or forced
10M/100M, full/half duplex, and it is also able to
configure to 100BaseFX transmission mode.
Using an EEPROM or pull up/down resistors on
specified pins can configure the desired options.
IP175A LF does not support “forced 10M half
mode”.
IP175A LF supports two MII ports for router
application, which supports 4 LAN ports and one
WAN port. MII0 is for LAN traffic and MII1 is for
WAN traffic and no external PHY is needed. Both
MII can work in PHY mode and interface to the
external MAC in this application. The external
MAC can monitor or configure IP175A LF by
accessing MII registers through SMI.
MII0 also can be configured to be MAC mode. It is
used to interface an external PHY to work as a
4+1 switch.
Copyright © 2004, IC Plus Corp.
1/60
February 20, 2006
IP175A LF-DS-R08
1 page  
Applications (continued)
Application 1: 5 TP port switch
Switch
IP175A LF
5 port
switch controller
PHY
0
PHY
1
PHY
2
PHY
3
PHY
4
5 TP port
Application 1: 5 FX port switch
Switch
IP175A LF
Fiber
MAU
0
Fiber
MAU
1
Fiber
MAU
2
Fiber
MAU
3
Fiber
MAU
4
5 FX port
IP175A LF
Preliminary DawtawwS.DhaetaeStheet4U.com
Use 5 builtin PHY.
MII0 and MII1 ports are not
used.
Use 5 external fiber MAU.
MII0 and MII1 ports are not
used.
Copyright © 2004, IC Plus Corp.
5/60
February 20, 2006
IP175A LF-DS-R08
5 Page 
IP175A LF
Preliminary DawtawwS.DhaetaeStheet4U.com
Pin Descriptions (continued)
Pin no.
Label
Type
Description
External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0)
81
MII0_TXCLK
O MII transmit clock
80, 79,
78, 77
TXD0_0, TXD0_1, IPL2 MII transmit data
TXD0_2, TXD0_3
It is sampled at the rising edge of MII0_TXCLK.
76 TXEN0
IPL2 MII transmit enable
90 COL0
It is used to frame TXD0[3:0]. It is sampled at the rising edge of
MII0_TXCLK.
O MII collision
84 RXDV0
It is active when port 4 of switch controller is set to be half duplex
and a collision event happens.
O MII receive data valid
88, 87,
86, 85
89
RXD0_0, RXD0_1, O
RXD0_2, RXD0_3
MII0_RXCLK
O
It is used to frame RXD0[3:0]. It is sent out at the falling edge of
MII0_TXCLK.
MII receive data
It is sent out at the falling edge of MII0_TXCLK.
MII receive clock
There is no clock output in this mode.
Pin no.
Label
Type
Description
External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0)
81 MII0_TXCLK I MII transmit clock
It is an input clock and it is connected to MII_TXCLK of external PHY.
80, 79,
78, 77
TXD0_0, TXD0_1, O
TXD0_2, TXD0_3
MII transmit data
It is connected to MII_TXD of external PHY. It is sent out at the
rising edge of MII0_TXCLK.
76 TXEN0
O MII transmit enable
90 COL0
It is an output signal and is connected to MII_TXEN of external
PHY. It is sent out at the rising edge of MII0_TXCLK.
IPL2 MII collision
84 RXDV0
It is an input signal and is connected to the MII_COL of external PHY.
I MII receive data valid
88, 87,
86, 85
89
RXD0_0, RXD0_1, I
RXD0_2, RXD0_3
MII0_RXCLK
I
It is an input signal and is connected to the MII_RXDV of
external PHY. RXDV0 is used to frame RXD0[3:0].
Receive data
It is NRZ data and is connected MII_RXD[3:0] of external PHY. It
is received at the rising edge of MII0_RXCLK.
MII receive clock
Copyright © 2004, IC Plus Corp.
11/60
February 20, 2006
IP175A LF-DS-R08
11 Page | ||
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| PDF Descargar | [ Datasheet IP175ALF.PDF ] | |
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