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SSTUH32866 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 SSTUH32866은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 SSTUH32866 기능
기능 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
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SSTUH32866 데이터시트, 핀배열, 회로
SSTUH32866
www.DataSheet4U.com
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable
registered buffer with parity for DDR2 RDIMM applications
Rev. 01 — 13 May 2005
Product data sheet
1. General description
The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is
pending publication. The register is configurable (using configuration pins C0 and C1) to
two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated
as Register A or Register B on the DIMM.
The SSTUH32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUH32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA
package (13.5 mm × 5.5 mm).
The SSTUH32866 is identical to SSTU32866 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs)
while maintaining speed and signal integrity.
2. Features
s Configurable register supporting DDR2 Registered DIMM applications
s Higher output drive strength version of SSTU32866 optimized for high-capacitive load
nets
s Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing state
s Supports SSTL_18 data inputs
s Checks parity on the DIMM-independent data inputs
s Partial parity output and input allows cascading of two SSTUH32866s for correct parity
error processing
s Differential clock (CK and CK) inputs




SSTUH32866 pdf, 반도체, 판매, 대치품
Philips Semiconductors
SSTUH32866
www.DataSheet4U.com
1.8 V high-drive DDR2 configurable registered buffer with parity
RESET
CK
CK
D2, D3, D5, D6,
D8 to D14
VREF
11
C1
PAR_IN
LPS0
(internal node)
CE
D
CLK
R
D2, D3, D5, D6,
D8 to D14 11
PARITY
CHECK
D
CLK
R
0
1
D2, D3, D5, D6,
11 D8 to D14
Q2A, Q3A,
11 Q5A, Q6A,
Q8A to Q14A
11 Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
D
CLK
R
CE
D
CLK
R
1
0
PPO
QERR
C0
CLK
2-BIT
COUNTER
R
LPS1
(internal node)
D
CLK
R
0
1
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
9397 750 14199
Product data sheet
Rev. 01 — 13 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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SSTUH32866 전자부품, 판매, 대치품
Philips Semiconductors
SSTUH32866
www.DataSheet4U.com
1.8 V high-drive DDR2 configurable registered buffer with parity
6.2 Pin description
Table 2:
Symbol
GND
VDD
VREF
CK
CK
C0
C1
Pin description
Pin
B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
A3, T3
H1
J1
G6
G5
RESET
G2
CSR
DCS
D1 to D25
J2
H2
[1]
DODT
[1]
DCKE
[1]
PAR_IN
G1
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
PPO
[1]
A2
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE, QCKEA,
QCKEB
[1]
[1]
[1]
Type
ground input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
outputs
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
Description
ground
power supply voltage
input reference voltage
positive master clock input
negative master clock input
Configuration control inputs; Register A
or Register B and 1 : 1 mode or 1 : 2
mode select.
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
Chip select inputs (active LOW). Disables
D1 to D25 [2] outputs switching when both
inputs are HIGH.
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
Parity input. Arrives one clock cycle after
the corresponding data input.
Data outputs that are suspended by the
DCS and CSR control [3].
Partial parity out. Indicates odd parity of
inputs D1 to D25 [2].
Data output that will not be suspended by
the DCS and CSR control.
Data output that will not be suspended by
the DCS and CSR control.
Data output that will not be suspended by
the DCS and CSR control.
9397 750 14199
Product data sheet
Rev. 01 — 13 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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