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PDF SSTU32866 Data sheet ( Hoja de datos )
| Número de pieza | SSTU32866 | |
| Descripción | 1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SSTU32866
www.DataSheet4U.com
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity for DDR2 RDIMM applications
Rev. 01 — 09 July 2004
Objective data
1. Description
The SSTU32866 is a 1.8 V configurable register specifically designed for use on
DDR2 memory modules requiring a parity checking function. It is defined in
accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered
buffer, while adding the parity checking function in a compatible pinout. The JEDEC
standard for SSTU32866 is pending publication. The register is configurable (using
configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the
latter configuration can be designated as Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent
D-inputs and indicates whether a parity error has occurred on its open-drain QERR
pin (active-LOW). The convention is even parity, i.e., valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity
input bit.
The SSTU32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA
package (13.5 mm by 5.5 mm).
2. Features
s Configurable register supporting DDR2 Registered DIMM applications
s Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching
propagation delay; 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing
state
s Supports SSTL_18 data inputs
s Checks parity on the DIMM-independent data inputs
s Partial parity output and input allows cascading of two SSTU32866s for correct
parity error processing
s Differential clock (CK and CK) inputs
s Supports LVCMOS switching levels on the control and RESET inputs
s Single 1.8 V supply operation
s Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package
1 page  
Philips Semiconductors
6. Functional description
SSTU32866
1.8 V DDR2 configurable registered buffer with parity
www.DataSheet4U.com
9397 750 12145
Objective data
The SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity,
designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS
drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTU32866 operates from a differential clock (CK and CK). Data are registered
at the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The SSTU32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent
D-inputs and indicates whether a parity error has occurred on its open-drain QERR
pin (active-LOW). The convention is even parity, i.e., valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity
input bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this
configuration, parity is checked on the PAR_IN input which arrives one cycle after the
input data to which it applies. The partial-parity-out (PPO) and QERR signals are
produced three cycles after the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of
the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity,
which arrives one cycle after the data input to which it applies, is checked on the
PAR_IN input of the first device. The PPO and QERR signals are produced on the
second device three clock cycles after the corresponding data inputs. The PPO
output of the first register is cascaded to the PAR_IN of the second register. The
QERR output of the first register is left floating and the valid error information is
latched on the QERR output of the second register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two
clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE,
DCS, DODT, and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the
differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing
states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW,
the Qn and PPO outputs will function normally. The RESET input has priority over the
DCS and CSR control and when driven LOW will force the Qn and PPO outputs LOW,
and the QERR output HIGH. If the DCS control functionality is not desired, then the
Rev. 01 — 09 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 27
5 Page 
Philips Semiconductors
SSTU32866
1.8 V DDR2 configurable registered buffer with parity
www.DataSheet4U.com
Table 9:
Symbol
IOH
IOL
Tamb
Recommended operating conditions…continued
Parameter
Conditions
HIGH-level output current
LOW-level output current
operating ambient temperature
in free air
Min
-
-
0
Nom
-
-
-
Max
−8
8
+70
Unit
mA
mA
°C
[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential
inputs must not be floating, unless RESET is LOW.
9. Static characteristics
Table 10: DC electrical characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol Parameter
Conditions
VOH HIGH-level output voltage IOH = −6 mA; VDD = 1.7 V
VOL LOW-level output voltage IOL = 6 mA; VDD = 1.7 V
Ii input current
all inputs; Vi = VDD or GND;
VDD = 1.9 V
IDD static standby current
RESET = GND; Io = 0 mA;
VDD = 1.9 V
static operating current
RESET = VDD; Io = 0 mA;
VDD = 1.9 V; Vi = VIH(AC) or VIL(AC)
IDDD
dynamic operating current,
clock only
RESET = VDD;
Vi = VIH(AC) or VIL(AC); CK and CK
switching at 50% duty cycle.
Io = 0 mA; VDD = 1.8 V
dynamic operating current,
per each data input, 1:1 mode
RESET = VDD;
Vi = VIH(AC) or VIL(AC); CK and CK
switching at 50% duty cycle. One
data input switching at half clock
frequency, 50% duty cycle.
Io = 0 mA; VDD = 1.8 V
dynamic operating current,
per each data input, 1:2 mode
RESET = VDD;
Vi = VIH(AC) or VIL(AC); CK and CK
switching at 50% duty cycle. One
data input switching at half clock
frequency, 50% duty cycle.
Io = 0 mA; VDD = 1.8 V
Ci input capacitance,
data and CSR inputs
Vi = VREF ± 250 mV; VDD = 1.8 V
input capacitance,
CK and CK inputs
input capacitance,
RESET input
VICR = 0.9 V; Vi(p-p) = 600 mV;
VDD = 1.8 V
Vi = VDD or GND; VDD = 1.8 V
Min
Typ Max
Unit
1.2 -
-
V
- - 0.5 V
- - ±5 µA
- - 100 µA
- - 40 mA
- 16 - µA /
MHz
- 11 - µA /
MHz
- 19 - µA /
MHz
2.5 -
2-
3-
3.5 pF
3 pF
4 pF
9397 750 12145
Objective data
Rev. 01 — 09 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 27
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| Páginas | Total 27 Páginas | |
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