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부품번호 | ICSSSTU32866 기능 |
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기능 | 25-Bit Configurable Registered Buffer | ||
제조업체 | Integrated Circuit System | ||
로고 | |||
Integrated
Circuit
Systems, Inc.
25-Bit Configurable Registered Buffer
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM logic solution with
ICS97U877
Product Features:
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on CSR# and
RESET# inputs
• Low voltage operation
VDD = 1.7V to 1.9V
• Available in 96 BGA package
Functionality Truth Table
I nputs
Outp uts
RST# DCS# CSR# CK
CK#
Dn,
DODT,
DCK E
Qn
QCS#
QODT,
QCKE
HLL
LL LL
HLL
HHL H
H
L
L L or H L or H X
Q0 Q0 Q0
HLH
LL LL
HLH
HHL H
H
L
H L or H L or H X
Q0 Q0 Q0
HHL
LL HL
HHL
HHHH
H H L L or H L or H X Q0 Q0 Q0
HHH
L Q0 H L
HHH
H Q0 H
H
H H H L or H L or H X Q0 Q0 Q0
L
X or X or X or X or X or
Floating Floating Floating Floating Floating
L
L
L
ICSSSTU32866
Advance Information
www.DataSheet4U.com
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96 Ball BGA
(Top View)
0850—08/27/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICSSSTU32866
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Ball Assignment
Terminal Name
GND
VDD
VREF
ZOH
ZOL
CK
CK
C0, C1
RST#
CSR#, DCS#
D1 - D25
DODT
DCKE
Q1 - Q25
QCS#
QODT
QCKE
PPO
PAR_IN
QERR#
Description
Electrical
Characteristics
Ground
Ground input
Power supply voltage
1.8V nominal
Input reference voltage
0.9V nominal
Reserved for future use
Input
Reserved for future use
Input
Positive master clock input
Differential input
Negative master clock input
Differential input
Configuration control inputs
LVCMOS inputs
Asynchronous reset input - resets registers and disables VREF data and
clock differential-input receivers
LVCMOS input
Chip select inputs - disables D1 - D24 outputs switching when both inputs
are high
SSTL_18 input
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK#
SSTL_18 input
The outputs of this register bit will not be suspended by the DCS# and
CSR# control
SSTL_18 input
The outputs of this register bit will now be suspended by the DCS# and
CSR# control
SSTL_18 input
Data ouputs that are suspended by the DCS# and CSR# control
1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
Partial parity out indicates off parity of inputs D1 - D25.
1.8V CMOS
Parity input arrives one clock cycle after the corresponding data input
SSTL_18 input
Output error bit-generated one clock cycle after the corresponding data Open drain
output
output
0850—08/27/03
4
4페이지 ICSSSTU32866
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Parity Functionality Block Diagram
RST#
VREF
DATA
INPUT*
CK
CK#
PAR_IN
Parity
Logic
DATA
OUTPUT*
PPO
QERR#
* Register Configurations
DATA INPUT: DATA OUTPUT: CO
D2, D3, D5, D6, D2, D3, D5, D6,
D8 - D25
D8 - D25
0
D2, D3, D5, D6, D2, D3, D5, D6,
D8 - D14
D8 - D14
0
D1 - D6, D8 - D1 - D6, D8 -
D10, D12, D13 D10, D12, D13
1
CI
0
1
1
0850—08/27/03
7
7페이지 | |||
구 성 | 총 13 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
ICSSSTU32864 | 25-Bit Configurable Registered Buffer | ICS |
ICSSSTU32866 | 25-Bit Configurable Registered Buffer | Integrated Circuit System |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |