FQV255 Datasheet PDF - High Bandwidth Access
| Part Number | FQV255 | |
| Description | 3.3 Volt Synchronous x18 First-In/First-Out Queue | |
| Manufacturers | High Bandwidth Access | |
| Logo |  |
|
|
There is a preview and FQV255 download ( pdf file ) link at the bottom of this page. Total 31 Pages | ||
Preview 1 page No Preview Available !
FQV2105 · FQV295 · FQV285 · FQV275 · FQwV2w6w5.D·aFtaQShVe2e5t45U.com
FlexQTMII
3.3 Volt Synchronous x18 First-In/First-Out Queue
Memory Configuration
262,144 x 18
131,072 x 18
65,536 x 18
32,768 x 18
16,384 x 18
8,192 x 18
Device
FQV2105
FQV295
FQV285
FQV275
FQV265
FQV255
Key Features
• Industry leading First-In/First-Out Queues (up to 133MHz)
• Write cycle time of 7.5ns independent of Read cycle time
• Read cycle time of 7.5ns independent of Write cycle time
• 3.3V power supply
• 5V input tolerant on all control and data input pins
• 5V output tolerant on all flags and data output pins
• Master Reset clears all previously programmed configurations including Write and Read pointers
• Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
• First Word Fall Through (FWFT) and Standard Timing modes
• Presets for eight different Almost Full and Almost Empty offset values
• Parallel/Serial programming of PRAF and PRAE offset values
• Full, Empty, Almost Full, Almost Empty, and Half Full indicators
• Asynchronous output enable tri-state data output drivers
• Data retransmission
• Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 - pin Slim Thin Quad Flat Pack (STQFP)
• (0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above
• (-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ II offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory
configurations (from 8,192 x 18 to 262,144 x 18). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.
In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode.
3F218C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 1 of 31
|
| |
 
FQV2105 · FQV295 · FQV285 · FQV275 · FQwV2w6w5.D·aFtaQShVe2e5t45U.com
FlexQTMII
Pin #
62
63
64
1
61
6,7,8,9,
10,11,12,13,
14,15,16,17,
18,19,20,21,
22,23
52
51
49
48,47,45,44,
42,41,40,38,
37,36,35,34,
32,31,29,28,
26,25
60
Pin Name
Master Reset
Partial Reset
Write Clock
Write Enable
Load Enable
Data Inputs
Read Clock
Read Enable
Output Enable
Data Outputs
First Word Fall
Through/Serial
Data Input
Pin Symbol
MRST
PRST
WCLK
WEN
LOAD
Input/Output
Input
Input
Input
Input
Input
Description
Master Reset is required to initialize Write and Read pointers to the
first position of the queue by setting MRST low. In Standard
mode, FULL and PRAF will go high; EMPTY and PRAE will go
low. In FWFT mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous programmed
configurations will not be maintained.
Partial Reset is required to initialize Write and Read pointers to the
first position of the queue by setting PRST low. In Standard mode,
FULL and PRAF will go high; EMPTY and PRAE will go low.
In FWFT mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous programmed
configurations will be maintained.
Writes data into queue during low to high transitions of WCLK if
WEN is set to low.
Controls write operation into queue or offset registers during low to
high transition of WCLK.
During Master Reset, set LOAD low to select parallel
programming or one of eight default offset values. Set LOAD high
to select serial programming or one of eight default offset values.
After Master Reset, LOAD controls write/read, to/from offset
registers during low to high transition of WCLK/RCLK
respectively. Use in conjunction with WEN / REN .
D17 - 0
Input
18 - bit wide input data bus.
RCLK
REN
OE
Input
Input
Input
Reads data from queue during low to high transitions of RCLK if
REN is set to low.
Controls read operation from queue or offset registers during low to
high transition of RCLK.
Setting OE low activates the data output drivers. Setting OE high
deactivates the data output drivers (High-Z).
Q17 - 0
FWFT/SDI
Output
18 - bit wide output data bus.
Input
Selects FWFT timing or Standard timing mode during Master
Reset. After Master Reset, if serial programming is selected
( LOAD = high), FWFT/SDI is used as the serial data input for the
offset registers. Serial data is written during the low to high
transition of WCLK. Use in conjunction with SDEN .
Table 1. Pin Descriptions
3F218C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 5 of 31
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FQV255 electronic component. |
| Information | Total 31 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FQV255.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| FQV255 | The function is 3.3 Volt Synchronous x18 First-In/First-Out Queue. High Bandwidth Access | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
FQV2
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||