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PDF BUK9MHH-65PNN Data sheet ( Hoja de datos )
| Número de pieza | BUK9MHH-65PNN | |
| Descripción | Dual TrenchPLUS FET Logic Level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
Rev. 02 — 19 May 2010
www.DataSheet4U.com
Objective data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance Architecture (HPA) TrenchPLUS technology,
featuring very low on-state resistance, integrated current sensing transistors and over
temperature protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
FET1 and FET2 static characteristics
RDSon
drain-source
on-state
resistance
VGS = 5 V; ID = 10 A;
Tj = 25 °C; see Figure 15;
see Figure 16
ID/Isense
ratio of drain
current to sense
current
Tj = 25 °C; VGS = 5 V;
see Figure 17
V(BR)DSS
drain-source
breakdown
voltage
ID = 250 µA; VGS = 0 V;
Tj = 25 °C
Min Typ Max Unit
- 9.8 11.5 mΩ
6193 6881 7569 A/A
65 - - V
1 page  
NXP Semiconductors
www.DataSheet4U.com
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
103
ID
(A)
102
10
1
10−1
10−2
10−1
Limit RDSon = VDS / ID
001aal760
tp = 10 μs
100 μs
1 ms
DC 10 ms
100 ms
1 10 102
VDS (V)
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-sp)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
FET1
FET2
mounted on a printed-circuit board; both
channels conducting; zero heat sink
area; see Figure 5
mounted on a printed-circuit board; both
channels conducting; 200 mm² copper
heat sink area; see Figure 6
mounted on a printed-circuit board; both
channels conducting; 400 mm² copper
heat sink area; see Figure 7
mounted on a printed-circuit board; one
channel conducting; zero heat sink
area; see Figure 5
mounted on a printed-circuit board; one
channel conducting; 200 mm² copper
heat sink area; see Figure 6
mounted on a printed-circuit board; one
channel conducting; 400 mm² copper
heat sink area; see Figure 7
Min Typ Max Unit
- - 25 K/W
- - 25 K/W
- 73 - K/W
- 60 - K/W
- 51 - K/W
- 105 - K/W
- 90 - K/W
- 70 - K/W
BUK9MHH-65PNN
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 19 May 2010
© NXP B.V. 2010. All rights reserved.
5 of 16
5 Page 
NXP Semiconductors
www.DataSheet4U.com
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
5
VGS
(V)
4
3
001aal818
VDS = 14 V
VDS = 52 V
2
1
0
0 10 20 30 40 50
QG (nC)
104
C
(pF)
103
102
003aae483
Ciss
Coss
Crss
10
10-1
1
10 102
VDS (V)
Fig 19. Gate-source voltage as a function of turn-on
gate charge; typical values, FET1 and FET2
60
IS
(A)
45
Fig 20. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values, FET1 and FET2
001aal614
30
15
0
0 0.5 1.0 1.5
VSD (V)
Fig 21. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1
and FET2
BUK9MHH-65PNN
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 19 May 2010
© NXP B.V. 2010. All rights reserved.
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