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PDF PCA9601 Data sheet ( Hoja de datos )
| Número de pieza | PCA9601 | |
| Descripción | Dual bidirectional bus buffer | |
| Fabricantes | NXP Semiconductors | |
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PCA9601
Dual bidirectional bus buffer
Rev. 01 — 28 May 2010
www.DataSheet4U.com
Product data sheet
1. General description
The PCA9601 is designed to isolate I2C-bus capacitance, allowing long buses to be
driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9601 is a
higher-speed version of the P82B96 and a higher drive version of the PCA9600 that
allows many more Fast-mode Plus (Fm+) slaves on remote daughter cards in applications
with temperature range of 0 °C to 85 °C.
It creates a non-latching, bidirectional, logic interface between a normal I2C-bus and a
range of other higher capacitance or different voltage bus configurations. It can operate at
speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode
Plus specifications.
The PCA9601 features temperature-stabilized logic voltage levels at its SX/SY interface
making it suitable for interfacing with buses that have non I2C-bus-compliant logic levels
such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.
15 mA drive capability over 0 °C to 85 °C at SX/SY allows driving a 5 V Fm+ bus with
470 pF loading.
The separation of the bidirectional I2C-bus signals into unidirectional TX and RX signals
enables the SDA and SCL signals to be transmitted via balanced transmission lines
(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX
signals may be connected together to provide a normal bidirectional signal.
2. Features and benefits
Bidirectional data transfer of I2C-bus signals
15 mA SX/SY sink capability yields 5 V Fm+ bus rise time with 470 pF loads
Isolates capacitance allowing > 400 pF on SX/SY side and 4000 pF on TX/TY side
1 MHz operation on up to 20 meters of wire (see AN10658)
Supply voltage range of 2.5 V to 15 V with I2C-bus logic levels on SX/SY side
independent of supply voltage
Splits I2C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths
Low power supply current
ESD protection exceeds 4500 V HBM per JESD22-A114, 450 V MM per
JESD22-A115, and 1400 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8 and TSSOP8 (MSOP8)
1 page  
NXP Semiconductors
www.DataSheet4U.com
PCA9601
Dual bidirectional bus buffer
7.2 High drive, long distance side
The logic level on RX is determined from the power supply voltage VCC of the chip. Logic
LOW is below 40 % of VCC, and logic HIGH is above 55 % of VCC (with a typical switching
threshold just slightly below half VCC).
TX is an open-collector output without ESD protection diodes to VCC. It may be connected
via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I2C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I2C-bus pin SX is below 0.425 V. A
logic LOW at RX will cause I2C-bus pin SX to be pulled to a logic LOW level in accordance
with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I2C-bus by a LOW at RX is typically 0.64 V
when sinking 1 mA.
If the supply voltage VCC fails, then neither the I2C-bus nor the TX output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without VCC present. The input configuration on SX and RX also
presents no loading of external signals when VCC is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including VCC = 0 V.
7.3 Connections to other bus buffers
Two or more SX or SY I/Os must not be interconnected. The PCA9601 design does not
support this configuration. Bidirectional I2C-bus signals do not allow any direction control
pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid
latching of this buffer. A ‘regular I2C-bus LOW’ applied at the RX/RY of a PCA9601 will be
propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special
‘buffered LOW’ is applied to the SX/SY of another PCA9601, that second PCA9601 will
not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it to its TX/TY output.
The SX/SY side of PCA9601 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side
of PCA9517, etc. The SX/SY side is only intended for, and compatible with, the normal
I2C-bus logic voltage levels of I2C-bus master and slave chips, or even TX/RX signals of a
second PCA9601 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard
I2C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the
interconnection of the TX/RX and TY/RY I/O pins to other PCA9601s, for example in a
star or multipoint configuration with the TX/RX and TY/RY I/O pins on the common bus
and the SX/SY side connected to the line card slave devices. For more details see
Application Note AN10658, “Sending I2C-bus signals via long communication cables”.
PCA9601_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 28 May 2010
© NXP B.V. 2010. All rights reserved.
5 of 31
5 Page 
NXP Semiconductors
www.DataSheet4U.com
PCA9601
Dual bidirectional bus buffer
VCC
≤ 1 mA
Vref
Fig 4. Equivalent circuit at SX/SY
SX (SY)
002aac838
800
VOL
(mV)
700
600
(1)
(2)
002aac839
500
400
−50 −25
0
25 50 75 100 125
Tj (°C)
VOL at SX typical and limits over temperature.
(1) Maximum.
(2) Typical.
Fig 5. VOL as a function of junction temperature
(IOL = 0.3 mA)
600
VIL
(mV)
500
001aai060
400
300
200
−50 −25
0
25 50 75 100 125
Tj (°C)
Fig 7.
VIL at SX changes over temperature range.
VIL as a function of junction temperature;
maximum values
800
VOL
(mV)
700
(1)
(2)
002aac840
600
500
400
−50 −25
0
25 50 75 100 125
Tj (°C)
VOL at SX typical and limits over temperature.
(1) Maximum.
(2) Typical.
Fig 6. VOL as a function of junction temperature
(IOL = 3 mA)
600
VIH
(mV)
500
001aai061
400
300
200
−50 −25
0
25 50 75 100 125
Tj (°C)
Fig 8.
VIH at SX changes over temperature range.
VIH as a function of junction temperature;
minimum values
PCA9601_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 28 May 2010
© NXP B.V. 2010. All rights reserved.
11 of 31
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| PDF Descargar | [ Datasheet PCA9601.PDF ] | |
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