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부품번호 AD5748 기능
기능 Industrial Current/Voltage Output Driver
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AD5748 데이터시트, 핀배열, 회로
Industrial Current/Voltage Output Driverwww.DataSheet4U.com
with Programmable Ranges
AD5748
FEATURES
Current output ranges: 4 mA to 21 mA, 0 mA to 21 mA
±0.15% FSR total unadjusted error (TUE)
±5 ppm/°C FSR typical output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10.5 V, ±10.5 V
±0.05% FSR total unadjusted error (TUE)
±3 ppm/°C FSR output drift
Flexible serial digital interface
On-chip output fault detection
PEC error checking
Asynchronous CLEAR function
Flexible power-up condition to 0 V or tristate
Power supply range
AVDD: +12 V (± 10%) to +24 V (± 10%)
AVSS: −12 V (± 10%) to −24 V (± 10%)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Process control
Actuator control
PLCs
GENERAL DESCRIPTION
The AD5748 is a single-channel, low cost, precision, voltage/
current output driver with hardware or software programmable
output ranges. The software ranges are configured via an SPI-/
MICROWIRE™-compatible serial interface. The AD5748 targets
applications in PLC and industrial process control. The analog
input to the AD5748 is provided from a low voltage, single-supply,
digital-to-analog converter (DAC) and is internally conditioned
to provide the desired output current/voltage range. The analog
input range is 0 V to 4.096 V.
The output current range is programmable across two current
ranges: 4 mA to 21 mA and 0 mA to 21 mA.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V
output range.
Analog outputs are short-circuit and open-circuit protected and
can drive capacitive loads of 2 μF and inductive loads of 0.1 H.
The device is specified to operate with a power supply range from
±12 V to ±24 V. Output loop compliance is 0 V to AVDD − 2.75 V.
The flexible serial interface is SPI- and MICROWIRE-compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications. The interface also
features an optional PEC error checking feature using CRC-8
error checking, useful in industrial environments where data
communication corruption can occur.
The device also includes a power-on-reset function, ensuring
that the device powers up in a known state (0 V or tristate),
and a asynchronous CLEAR pin that sets the outputs to zero
scale/midscale voltage output or the low end of the selected
current range.
An HW SELECT pin is used to configure the part for hardware
or software mode on power-up.
Note that the plots in the Typical Performance Characteristics
section of this data sheet contain information on the standard
ranges, as released in the AD5750/AD5750-1 data sheet. Although
the overranges have been tested, new plots were not generated
and substitution data was used for plotting purposes.
Table 1. Related Device
Part Number Description
AD5422
Single-channel, 16-bit, serial input current
source and voltage output DAC
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.




AD5748 pdf, 반도체, 판매, 대치품
AD5748
www.DataSheet4U.com
SPECIFICATIONS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter1
INPUT VOLTAGE RANGE
VIN
Input Leakage Current
REFERENCE INPUT
Reference Input Voltage
Min
−1
Input Leakage Current
VOLTAGE OUTPUT, VOUT
Output Voltage Ranges
Accuracy
Total Unadjusted Error (TUE)2
Relative Accuracy (INL)
Bipolar Zero Error (Offset at
Midscale)
Bipolar Zero Error TC3
Zero-Scale Error
Zero-Scale Error TC3
Zero-Scale/Offset Error
Offset Error TC3
Gain Error
Gain Error TC3
Full-Scale Error
Full-Scale Error TC3
VOLTAGE OUTPUT CHARACTERISTICS3
Headroom
Short-Circuit Current
Load
Capacitive Load Stability
RLOAD = ∞
RLOAD = 2 kΩ
RLOAD = ∞
DC Output Impedance
0 V to 5 V range, ¼ to ¾ Step
0 V to 5 V range, 40 mV Input Step
Slew Rate
Output Noise
−1
0
0
−10.5
−0.3
−0.1
−0.02
−10
−8
−10
−8
−5
−4
−3
−2.2
−0.05
−0.04
−0.05
−0.04
1
Typ
0 to 4.096
4.096
Max
+1
+1
5
10.5
+10.5
±0.05
±0.005
±0.5
±1.5
±0.5
±1
±0.5
±0.3
±2
±0.015
±0.5
±0.015
±1.5
15
+0.3
+0.1
+0.02
+10
+8
+10
+8
+5
+4
+3
+2.2
+0.05
+0.04
+0.05
+0.04
1.3
1
1
2
0.12
7
4.5
2
2.5
45.5
Rev. 0 | Page 4 of 32
Unit Test Conditions/Comments
Output unloaded
V
μA
V External reference needs to be exactly as
stated; otherwise, accuracy errors show
up as error in output
μA
V
V AVDD must have minimum 1.3 V
headroom
V AVDD/AVSS must have minimum 1.3 V
headroom
% FSR
% FSR
% FSR
mV
mV
ppm FSR/°C
mV
mV
ppm FSR/°C
mV
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
TA = 25°C
±10.5 V range
TA = 25°C, ±10.5 V range
±10.5 V range
±10.5 V range
TA = 25°C, ±10.5 V range
±10.5 V range
0 V to 10.5 V range
TA = 25°C, 0 V to 10.5 V range
0 V to 5 V range
TA = 25°C, 0 V to 5 V range
All ranges
TA = 25°C
All ranges
TA = 25°C
V
mA
nF
nF
μF
Ω
μs
μs
V/μs
μV rms
μV rms
Output unloaded
TA = 25°C
External compensation capacitor required;
see the Driving Inductive Loads section
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF
0.1 Hz to 10 Hz bandwidth
100 kHz bandwidth

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AD5748 전자부품, 판매, 대치품
AD5748www.DataSheet4U.com
TIMING CHARACTERISTICS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =
300 Ω. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7
t8
t9, t10
t11
t12
t13
Limit at TMIN, TMAX
20
8
8
5
10
5
5
5
1.5
5
40
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)
Minimum SYNC high time (write mode)
Data setup time
Data hold time
CLEAR pulse low/high activation time
Minimum SYNC high time (read mode)
SCLK rising edge to SDO valid (SDO CL = 15 pF)
RESET pulse low time
1 Guaranteed by characterization, but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
Rev. 0 | Page 7 of 32

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