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PDF SSTUB32868 Data sheet ( Hoja de datos )
| Número de pieza | SSTUB32868 | |
| Descripción | 1.8 V 28-bit 1 : 2 configurable registered buffer with parity | |
| Fabricantes | NXP Semiconductors | |
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SSTUB32868
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for
DDR2-800 RDIMM applications
Rev. 04 — 22 April 2010
Product data sheet
1. General description
The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUB32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it can be
configured for normal or high output drive strength, simply by tying input pin SELDR either
HIGH or LOW as needed. This allows use in different module designs varying from low to
high density designs by picking the appropriate drive strength to match net loading
conditions. Furthermore, the SSTUB32868 features two additional chip select inputs,
which allow more versatile enabling and disabling in densely populated memory modules.
Both added features (drive strength and chip selects) are fully backward compatible to the
JEDEC standard register.
The SSTUB32868 is packaged in a 176-ball, 8 × 22 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6 mm × 15 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2. Features and benefits
28-bit data register supporting DDR2
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)
Parity checking function across 22 input data bits
Parity out signal
Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
Meets or exceeds SSTUB32868 JEDEC standard speed performance
Supports up to 450 MHz clock frequency of operation
Programmable for normal or high output drive
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
1 page  
NXP Semiconductors
www.DataSheet4U.com
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUB32868ET/G
ball A1 SSTUB32868ET/S
index area 2 4 6 8
1357
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
002aac337
Transparent top view
Fig 3. Pin configuration for TFBGA176
SSTUB32868_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 22 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 30
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NXP Semiconductors
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SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
Table 5. Parity and standby function table
Inputs
RESET
DCS0[1]
DCS1[1]
CK
CK
HL X ↑ ↓
HL X ↑ ↓
HL X ↑ ↓
HL X ↑ ↓
HX L ↑ ↓
HX L ↑ ↓
HX L ↑ ↓
HX L ↑ ↓
HH H ↑ ↓
HX
X
L or H
L or H
L X or floating X or floating X or floating X or floating
∑ of inputs = H
(D1 to D28)
even
odd
even
odd
even
odd
even
odd
X
X
X
PAR_IN[2]
L
L
H
H
L
L
H
H
X
X
X or floating
Output
QERR[3][4]
H
L
L
H
H
L
L
H
QERR0[5]
QERR0
H
[1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2] PAR_IN arrives one clock cycle after the data to which it applies.
[3] This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
[4] QERR0 is the previous state of output QERR.
[5] If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on
the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus
two clock cycles or until RESET is driven LOW.
7.2 Functional information
The SSTUB32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to
1.9 V VDD operation.
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All
outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and
all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always
must be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be ensured between the two.
When entering reset, the register will be cleared and the data outputs will be driven LOW
quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
SSTUB32868_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 22 April 2010
© NXP B.V. 2010. All rights reserved.
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