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11LC080 데이터시트 PDF




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부품번호 11LC080 기능
기능 1K-16K UNI/O Serial EEPROM Family
제조업체 Microchip Technology
로고 Microchip Technology 로고


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11LC080 데이터시트, 핀배열, 회로
11AA010/11LC010
11AA020/11LC020
11AA040/11LC040
11AA080/11LC080
11AA160/11LC160
11AA161/11LC161
1K-16K UNI/O® Serial EEPROM Family Data Sheet
Features:
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current (max.) (I-temp)
• 128 x 8 through 2,048 x 8 Bit Organizations
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• 3-lead SOT-23 and TO-92 Packages
• 4-lead Chip Scale Package
• 8-lead PDIP, SOIC, MSOP, TDFN Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
Pin Function Table
Name
Function
SCIO
VSS
VCC
Serial Clock, Data Input/Output
Ground
Supply Voltage
Description:
The Microchip Technology Inc. 11AAXXX/11LCXXX
(11XX*) devices are a family of 1 Kbit through 16 Kbit
Serial Electrically Erasable PROMs. The devices are
organized in blocks of x8-bit memory and support the
patented** single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Low-voltage design permits operation down to 1.8V (for
11AAXXX devices), with standby and active currents of
only 1 uA and 1 mA, respectively.
The 11XX family is available in standard packages
including 8-lead PDIP and SOIC, and advanced pack-
aging including 3-lead SOT-23, 3-lead TO-92, 4-lead
Chip Scale, 8-lead TDFN, and 8-lead MSOP.
Package Types (not to scale)
MSOP
(MS)
PDIP/SOIC
(P, SN)
NC
NC
NC
VSS
1
2
3
4
8 VCC NC 1
7 NC NC 2
6
5
NC
SCIO
NC 3
Vss 4
8 VCC
7 NC
6 NC
5 SCIO
NC 1
NC 2
NC 3
VSS 4
TDFN
(MN)
SOT23
(TT)
8 VCC
7 NC VSS 3
6 NC
5 SCIO
2 VCC
1 SCIO
TO-92
(TO)
CS (Chip Scale)(1)
VCC 1
2 VSS
Vss
Vcc
SCIO
SCIO 3
4 NC
(Top down view,
balls not visible)
Note 1: Available in I-temp, “AA” only.
* 11XX is used in this document as a generic part number for the 11 series devices.
** Microchip’s UNI/O® Bus products are covered by some or all of the following patents issued in the U.S.A.: 7,376,020 & 7,788,430.
2011 Microchip Technology Inc.
DS22067J-page 1




11LC080 pdf, 반도체, 판매, 대치품
11XX
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = 2.5V to 5.5V
VCC = 1.8V to 2.5V
Automotive (E): VCC = 2.5V to 5.5V
TA = -40°C to +85°C
TA = -20°C to +85°C
TA = -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1 FBUS Serial bus frequency
10 100 kHz —
2 TE Bit period
10 100 µs —
3 TIJIT Input edge jitter tolerance —
±0.06
UI (Note 3)
4 FDRIFT Serial bus frequency drift
rate tolerance
±0.50 % per byte —
5 FDEV Serial bus frequency drift
limit
±5 % per —
command
6 TOJIT Output edge jitter
— ±0.25 UI (Note 3)
7 TR SCIO input rise time
(Note 1)
— 100 ns —
8 TF SCIO input fall time
(Note 1)
— 100 ns —
9 TSTBY Standby pulse time
600 —
µs —
10 TSS Start header setup time
10
µs —
11 THDR Start header low pulse 5 — µs —
time
12 TSP Input filter spike
suppression (SCIO)
— 50 ns (Note 1)
13 TWC Write cycle time
(byte or page)
— 5 ms Write, WRSR commands
— 10 ms ERAL, SETAL commands
14 — Endurance (per page)
1M — cycles 25°C, VCC = 5.5V (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total EnduranceModel which can be obtained on Microchip’s web site:
www.microchip.com.
3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
DS22067J-page 4
2011 Microchip Technology Inc.

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11LC080 전자부품, 판매, 대치품
11XX
3.0 BUS CHARACTERISTICS
3.1 Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11XX will reset and return to Standby
mode. Subsequently, a high-to-low transition on SCIO
(the first low pulse of the header) will return the device
to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of TSS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must per-
form a standby pulse before beginning a new com-
mand, regardless of which device is to be selected.
Note: After a POR/BOR event occurs, a low-
to-high transition on SCIO must be gen-
erated before proceeding with commu-
nication, including a standby pulse.
An example of two consecutive commands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1:
CONSECUTIVE COMMANDS EXAMPLE
SCIO
Standby Pulse(1)
Start Header
01010101
Device Address
10100000
SCIO
Start Header
01010101
Device Address
10100000
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
3.2 Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
FIGURE 3-2:
START HEADER
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
TSS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
SCIO
TSS THDR Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK NoSAK
2011 Microchip Technology Inc.
DS22067J-page 7

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부품번호상세설명 및 기능제조사
11LC080

1K-16K UNI/O Serial EEPROM Family

Microchip Technology
Microchip Technology

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