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PDF LPC2930 Data sheet ( Hoja de datos )
| Número de pieza | LPC2930 | |
| Descripción | ARM9 flashless microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC2930
ARM9 flashless microcontroller with CAN, LIN, and USB
Rev. 03 — 16 April 2010
Product data sheet
1. General description
The LPC2930 combine an ARM968E-S CPU core with two integrated TCM blocks
operating at frequencies of up to 125 MHz, Full-speed USB 2.0 Host/OTG/Device
controller, CAN and LIN, 56 kB SRAM, external memory interface, three 10-bit ADCs, and
multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, and
communication markets. To optimize system power consumption, the LPC2930 has a
very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.
2. Features and benefits
ARM968E-S processor running at frequencies of up to 125 MHz maximum.
Multilayer AHB system bus at 125 MHz with four separate layers.
On-chip memory:
Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data
TCM (DTCM).
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
8 kB ETB SRAM, also usable for code execution and data.
Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
Serial interfaces:
USB 2.0 full-speed Host/OTG/Device controller with dedicated DMA controller and
on-chip device PHY.
Two-channel CAN controller supporting FullCAN and extensive message filtering
Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, modem
control, and RS-485/EIA-485 (9-bit) support.
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
Two I2C-bus interfaces.
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
www.DataSheet4U.com
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
1 156
LPC2930FBD208
52 105
Fig 2. Pin configuration for LQFP208 package
002aae258
5.2 Pin description
5.2.1 General description
The LPC2930 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each,
port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each
function is assigned is controlled by the SFSP registers in the SCU. The functions
combined on each port pin are shown in the pin description tables in this section.
5.2.2 LQFP208 pin assignment
Table 3. LQFP208 pin assignment
Pin name
Pin Description
Function 0
(default)
Function 1
TDO
1[1] IEEE 1149.1 test data out
P2[21]/SDI2/
PCAP2[1]/D19
2[1] GPIO 2, pin 21 SPI2 SDI
P0[24]/TXD1/
3[1] GPIO 0, pin 24 UART1 TXD
TXDC1/SCS2[0]
P0[25]/RXD1/
RXDC1/SDO2
4[1] GPIO 0, pin 25 UART1 RXD
P0[26]/TXD1/SDI2 5[1]
GPIO 0, pin 26
-
P0[27]/RXD1/SCK2 6[1]
GPIO 0, pin 27
-
P0[28]/CAP0[0]/ 7[1] GPIO 0, pin 28 -
MAT0[0]
P0[29]/CAP0[1]/ 8[1] GPIO 0, pin 29 -
MAT0[1]
VDD(IO)
P2[22]/SCK2/
PCAP2[2]/D20
9
10[1]
3.3 V power supply for I/O
GPIO 2, pin 22
SPI2 SCK
Function 2
PWM2 CAP1
CAN1 TXD
CAN1 RXD
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
PWM2 CAP2
Function 3
EXTBUS D19
SPI2 SCS0
SPI2 SDO
SPI2 SDI
SPI2 SCK
TIMER0 MAT0
TIMER0 MAT1
EXTBUS D20
LPC2930_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 98
5 Page 
NXP Semiconductors
www.DataSheet4U.com
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
Table 3. LQFP208 pin assignment …continued
Pin name
Pin Description
Function 0
(default)
Function 1
Function 2
Function 3
P5[6]/D18/RI0
148[1] GPIO 5, pin 6
EXTBUS D18
UART0 RI
-
P4[14]/BLS2
149[1] GPIO 4, pin 14
EXTBUS BLS2
-
-
P0[5]/IN0[1]/
PMAT0[3]/D29
150[1] GPIO 0, pin 5
ADC0 IN1
PWM0 MAT3
EXTBUS D29
P5[14]/
151[1]
USB_SSPND1/RTS0
GPIO 5, pin 14
USB_SSPND1
UART0 RS
-
VDD(IO)
P0[6]/IN0[2]/
PMAT0[4]/D30
152
153[1]
3.3 V power supply for I/O
GPIO 0, pin 6
ADC0 IN2
PWM0 MAT4
EXTBUS D30
P0[7]/IN0[3]/
PMAT0[5]/D31
154[1] GPIO 0, pin 7
ADC0 IN3
PWM0 MAT5
EXTBUS D31
VDDA(ADC3V3)
JTAGSEL
155
156[1]
3.3 V power supply for ADC
TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan; pulled up internally.
VDDA(ADC5V0)
VREFP
157
158[4]
5 V supply voltage for ADC0 and 5 V reference for ADC0.
HIGH reference for ADC
VREFN
159[4] LOW reference for ADC
P0[8]/IN1[0]/TXDL0/ 160[5]
A20
GPIO 0, pin 8
ADC1 IN0
LIN0 TXD/ UART TXD EXTBUS A20
P0[9]/IN1[1]/
RXDL0/A21
161[5] GPIO 0, pin 9
ADC1 IN1
LIN0 RXD/ UART TXD EXTBUS A21
P0[10]/IN1[2]/
PMAT1[0]/A8
162[5] GPIO 0, pin 10
ADC1 IN2
PWM1 MAT0
EXTBUS A8
P0[11]/IN1[3]/
PMAT1[1]/A9
163[5] GPIO 0, pin 11
ADC1 IN3
PWM1 MAT1
EXTBUS A9
P2[14]/SDA1/
PCAP0[0]/BLS0
164[1] GPIO 2, pin 14
I2C1 SDA
PWM0 CAP0
EXTBUS BLS0
P2[15]/SCL1/
PCAP0[1]/BLS1
165[1] GPIO 2, pin 15
I2C1 SCL
PWM0 CAP1
EXTBUS BLS1
P3[2]/MAT3[0]/
PMAT2[2]/
USB_SDA1
166[1] GPIO 3, pin 2
TIMER3 MAT0
PWM2 MAT2
USB_SDA1
VDD(CORE)
VSS(CORE)
VSS(IO)
P4[3]/A11
167
168
169
170[1]
1.8 V power supply for digital core
ground for digital core
ground for I/O
GPIO 4, pin 3
EXTBUS A11
-
-
P3[3]/MAT3[1]/
PMAT2[3]/
USB_SCL1
171[1] GPIO 3, pin 3
TIMER3 MAT1
PWM2 MAT3
USB_SCL1
P5[3]/D11
172[1] GPIO 5, pin 3
EXTBUS D11
-
-
P0[12]/IN1[4]/
PMAT1[2]/A10
173[5] GPIO 0, pin 12
ADC1 IN4
PWM1 MAT2
EXTBUS A10
P4[19]/
USB_CONNECT2
174[1]
GPIO 4, pin 19
USB_CONNECT2 -
-
LPC2930_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 April 2010
© NXP B.V. 2010. All rights reserved.
11 of 98
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC2930.PDF ] | |
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