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부품번호 P89LV51RB2 기능
기능 8-bit 80C51 3 V low power 16/32/64 kB fash microcontroller
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P89LV51RB2 데이터시트, 핀배열, 회로
www.DataSheet4U.com
P89LV51RB2/RC2/RD2
8-bit 80C51 3 V low power 16/32/64 kB flash microcontroller
with 1 kB RAM
Rev. 05 — 15 December 2009
Product data sheet
1. General description
The P89LV51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and
1024 B of data RAM.
A key feature of the P89LV51RB2/RC2/RD2 is its X2 mode option. The design engineer
can choose to run the application with the conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the
throughput at the same clock frequency. Another way to benefit from this feature is to keep
the same performance by reducing the clock frequency by half, thus dramatically reducing
the EMI.
The flash program memory supports both parallel programming and in serial ISP. Parallel
programming mode offers gang-programming at high speed, reducing programming costs
and time to market. ISP allows a device to be reprogrammed in the end product under
software control. The capability to field/update the application firmware makes a wide
range of applications possible.
The P89LV51RB2/RC2/RD2 is also capable of IAP, allowing the flash program memory to
be reconfigured even while the application is running.
2. Features
I 80C51 CPU
I 3 V operating voltage from 0 MHz to 33 MHz
I 16/32/64 kB of on-chip flash user code memory with ISP and IAP
I Supports 12-clock (default) or 6-clock mode selection via software or ISP
I SPI and enhanced UART
I PCA with PWM and capture/compare functions
I Four 8-bit I/O ports with three high-current port 1 pins (16 mA each)
I Three 16-bit timers/counters
I Programmable watchdog timer
I Eight interrupt sources with four priority levels
I Second DPTR register
I Low EMI mode (ALE inhibit)
I TTL- and CMOS-compatible logic levels




P89LV51RB2 pdf, 반도체, 판매, 대치품
NXP Semiconductors
5. Pinning information
5.1 Pinning
www.DataSheet4U.com
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
P1.5/MOSI/CEX2 7
P1.6/MISO/CEX3 8
P1.7/SPICLK/CEX4 9
RST 10
P3.0/RXD 11
n.c. 12
P3.1/TXD 13
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
P3.5/T1 17
P89LV51RB2BA
P89LV51RD2FA
39 P0.4/AD4
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 EA
34 n.c.
33 ALE/PROG
32 PSEN
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
002aaa509
Fig 2. PLCC44 pin configuration
P89LV51RB2_RC2_RD2_5
Product data sheet
Rev. 05 — 15 December 2009
© NXP B.V. 2009. All rights reserved.
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P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 3. P89LV51RB2/RC2/RD2 pin description …continued
Symbol
Pin
Type
Description
TQFP44 PLCC44
P1.3/CEX0
43
5
I/O P1.3 — Port 1 bit 3.
I/O CEX0 — Capture/compare external I/O for PCA Module 0. Each
capture/compare module connects to a Port 1 pin for external
I/O. When not used by the PCA, this pin can handle standard I/O.
P1.4/SS/CEX1 44
6
I/O P1.4 — Port 1 bit 4.
I SS — Slave port select input for SPI.
I/O CEX1 — Capture/compare external I/O for PCA Module 1.
P1.5/MOSI/
1
7
I/O P1.5 — Port 1 bit 5.
CEX2
I/O MOSI — Master Output Slave Input for SPI.
I/O CEX2 — Capture/compare external I/O for PCA Module 2.
P1.6/MISO/
2
8
I/O P1.6 — Port 1 bit 6.
CEX3
I/O MISO — Master Input Slave Output for SPI.
I/O CEX3 — Capture/compare external I/O for PCA Module 3.
P1.7/SPICLK/ 3 9 I/O P1.7 — Port 1 bit 7.
CEX4
I/O SPICLK — Serial clock input/output for SPI.
I/O CEX4 — Capture/compare external I/O for PCA Module 4.
P2.0 to P2.7
I/O with
internal
pull-up
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins are pulled HIGH by the internal pull-ups
when ‘1’s are written to them and can be used as inputs in this
state. As inputs, Port 2 pins that are externally pulled LOW will
source current (IIL) because of the internal pull-ups. Port 2 sends
the high-order address byte during fetches from external
program memory and during accesses to external Data Memory
that use 16-bit address (MOVX@DPTR). In this application, it
uses strong internal pull-ups when transitioning to ‘1’s. Port 2
also receives some control signals and a partial of high-order
address bits during the external host mode programming and
verification.
P2.0/A8
18
24
I/O
P2.0 — Port 2 bit 0.
O A8 — Address bit 8.
P2.1/A9
19
25
I/O
P2.1 — Port 2 bit 1.
O A9 — Address bit 9.
P2.2/A10
20
26
I/O
P2.2 — Port 2 bit 2.
O A10 — Address bit 10.
P2.3/A11
21
27
I/O
P2.3 — Port 2 bit 3.
O A11 — Address bit 11.
P2.4/A12
22
28
I/O
P2.4 — Port 2 bit 4.
O A12 — Address bit 12.
P2.5/A13
23
29
I/O
P2.5 — Port 2 bit 5.
O A13 — Address bit 13.
P2.6/A14
24
30
I/O
P2.6 — Port 2 bit 6.
O A14 — Address bit 14.
P89LV51RB2_RC2_RD2_5
Product data sheet
Rev. 05 — 15 December 2009
© NXP B.V. 2009. All rights reserved.
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P89LV51RB2

8-bit 80C51 3 V low power 16/32/64 kB fash microcontroller

NXP Semiconductors
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