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PDF PCA9575 Data sheet ( Hoja de datos )
| Número de pieza | PCA9575 | |
| Descripción | level translating - low voltage GPIO | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 03 — 9 November 2009
Product data sheet
1. General description
The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between
1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports
can be configured as an input or output independent of each other and default on start-up
to inputs.
I/O expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum; for example in battery powered mobile applications and
clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to
providing a flexible set of GPIOs, it simplifies interconnection of a processor running at
one voltage level to I/O devices operating at a different (usually higher) voltage level.
PCA9575 has built-in level shifting feature that makes these devices extremely flexible in
mixed signal environments where communication between incompatible I/Os is required.
The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can
operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or
pull-down feature for I/Os is also provided.
The output stage consists of two banks each of 8-bit configuration registers, input
registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down
registers and polarity inversion registers. These registers allow the system master to
program and configure 16 GPIOs through the I2C-bus.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read registers can be inverted with the Polarity
Inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s
at the same time even if they have different individual I2C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal
1 page  
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
read pulse
configuration
register
DQ
FF
CK Q
DQ
FF
CK
output port
register
input port
register
DQ
FF
CK
VDD(IO)
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
100 kΩ
Q1
Q2 ESD
protection
diode
INTERRUPT
MASK
output port
register data
VDD(IO)
P0_0 to P0_7
P1_0 to P1_7
VSS
input port
register data
to INT
data from
shift register
write polarity
pulse
polarity
inversion
register
DQ
FF
CK
Fig 2. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
polarity
inversion
register data
002aad566
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
5 of 38
5 Page 
NXP Semiconductors
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.2 Register 1 - Input port 1 register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by the Configuration register. Writes to
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
Table 5. Register 1 - Input port 1 register (address 01h) bit description
Bit Symbol Access Value
Description
7 IO1.7 read only X
determined by externally applied logic level
6 IO1.6 read only X
5 IO1.5 read only X
4 IO1.4 read only X
3 IO1.3 read only X
2 IO1.2 read only X
1 IO1.1 read only X
0 IO1.0 read only X
7.6.3 Register 2 - Polarity inversion port 0 register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 6. Register 2 - Polarity Inversion port 0 register (address 02h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N0.7 R/W 0* inverts polarity of Input port 0 register data
6 N0.6 R/W 0*
5 N0.5 R/W 0*
0 = Input port 0 register data retained (default value)
1 = Input port 0 register data inverted
4 N0.4 R/W 0*
3 N0.3 R/W 0*
2 N0.2 R/W 0*
1 N0.1 R/W 0*
0 N0.0 R/W 0*
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
11 of 38
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