|
|
|
부품번호 | ACE24C256 기능 |
|
|
기능 | Two-wire Serial EEPROM | ||
제조업체 | ACE Technology | ||
로고 | |||
www.DataSheet4U.com
ACE24C128/256
Technology
Two-wire Serial EEPROM
Description
The ACE24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read-only
memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up
to 8 devices to share a common two-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
Features
z Low Operation Voltage: Vcc = 1.7V to 5.5V
z Internally Organized: 16,384 x 8(128K), 32,768 x 8(256K)
z Two-wire Serial Interface
z Schmitt Trigger, Filtered Inputs for Noise Suppression
z Bi-directional Data Transfer Protocol
z 1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility
z Write Protect Pin for Hardware Data Protection
z 64-byte Page Write Modes (Partial Page Writes are Allowed)
z Self-timed Write Cycle (5 ms max)
z High-reliability - Endurance: 1,000,000 Write Cycles
- Data Retention: 100 Years
z PDIP-8,SOP-8,TSSOP-8 ROHS compliant Packages
z Wafer Sales: available in inked wafer Form
Absolute Maximum Ratings
Operating Temperature
Storage Temperature
-55℃ to +125℃
-65℃ to +150℃
Voltage on Any Pin with Respect to Ground -1.0V to +7.0V
Maximum Operating Voltage
6.25V
DC Output Current
5.0 mA
*Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
VER 1.2 1
www.DataSheet4U.com
ACE24C128/256
Technology
Two-wire Serial EEPROM
Ordering information
Selection Guide
ACE24C128/256 XX + X H
Halogen-free
U : Tube
T : Tape and Reel
Pb - free
DP : PDIP-8
FM : SOP-8
TM : TSSOP-8
Serial Clock (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
Serial Data (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device/Page Addresses (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for
hardware compatibility with other ACE24CXXX/ACE24CXXX devices. When the pins are hardwired,
as many as eight 128K/256K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).If the pins are left floating, the A2, A1 and A0
pins will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane is <
3pF, if coupling is > 3pF recommends connecting the address pins to GND.
Write Protect (WP):
The ACE24C128/256 has a Write Provides hardware data protection. The WP pin allows normal write
operations when connected to ground (GND). When the Write Protect pin is connected to Vcc. All write
operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled is
< 3pF , if coupling is > 3pF, recommends connecting the pins to GND. Switching WP to Vcc prior to a
write operation creates a software write protected function.
Write Protect Description
WP Pin Status
Part of the Array Protected
ACE24C128
ACE24C256
WP=VCC
Full (128K) Memory
Full (256K) Memory
WP=GND
Normal Read/Write Operations
VER 1.2 4
4페이지 www.DataSheet4U.com
ACE24C128/256
Technology
Two-wire Serial EEPROM
Device Operation
Clock and Data Transitions:
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only
during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (refer to Figure 5).
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Figure 5).
Acknowledge:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Standby Mode :
The ACE24C128/256 features a low-power standby mode which is enabled: (a) upon power-up and (b)
after the receipt of the stop bit and the completion of any internal operations.
Memory Reset :
After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high and then.
3. Create a start condition as SDA is high.
Bus Timing
Figure 2.SCL: Serial Clock, SDA: Serial Data I/O
VER 1.2 7
7페이지 | |||
구 성 | 총 16 페이지수 | ||
다운로드 | [ ACE24C256.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
ACE24C256 | Two-wire Serial EEPROM | ACE Technology |
ACE24C256B | Two-wire Serial EEPROM | ACE Technology |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |