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PDF MPC8308 Data sheet ( Hoja de datos )
| Número de pieza | MPC8308 | |
| Descripción | PowerQUICC II Pro Processor Hardware Specification | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Document Number:wwMwP.DaCta8Sh3ee0t48U.EcoCm
Rev. 1, 07/2010
MPC8308 PowerQUICC II Pro
Processor Hardware Specification
This document provides an overview of the MPC8308
features and its hardware specifications, including a block
diagram showing the major functional components. The
MPC8308 is a cost-effective, low-power, highly integrated
host processor. The MPC8308 extends the PowerQUICC
family, adding higher CPU performance, additional
functionality, and faster interfaces while addressing the
requirements related to time-to-market, price, power
consumption, and package size.
NOTE
The information provided in this document is
preliminary and is based on estimates only and refers to
the pre-silicon phase, with no device characterization
done. Freescale reserves the right to change the
contents of this document as appropriate.
1 Overview
Figure 1 shows the major functional units within the
MPC8308. The e300 core in the MPC8308, with its 16
Kbytes of instruction and 16 Kbytes of data cache,
implements the Power Architecture user instruction set
architecture and provides hardware and software debugging
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8. Ethernet: Three-Speed Ethernet, MII Management . 15
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 24
11. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12. Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 43
13. Enhanced Secure Digital Host Controller (eSDHC) . 47
14. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
20. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 62
21. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
22. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
23. System Design Information . . . . . . . . . . . . . . . . . . . 81
24. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85
25. Document Revision History . . . . . . . . . . . . . . . . . . . 86
© Freescale Semiconductor, Inc., 2010. All rights reserved.
1 page  
Electwriwcawl.CDahtaSrahecette4rUis.ctoicms
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device
G/L/NVDD + 20%
G/L/NVDD + 5%
VIH G/L/NVDD
VSS
VSS – 0.3 V
VIL
VSS – 0.7 V
Note:
Not to Exceed 10%
of tinterface1
1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths.
Table 3. Output Driver Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
Local bus interface utilities signals
DDR2 signals1
DUART, system control, I2C, JTAG, eSDHC, GPIO,SPI, USB
42
18
42
NVDD = 3.3 V
GVDD = 1.8 V
NVDD = 3.3 V
eTSEC signals
42 LVDD = 2.5/3.3 V
1 Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).
For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
2.1.4 Power Sequencing
The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD, LVDD, and
NVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies
are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that
all input and output pins are actively driven and cause contention and excessive current. In order to avoid
actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before
the I/O voltage (GVDD, LVDD, and NVDD) and assert PORESET before the power supplies fully ramp up.
In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal
value before the I/O supplies reach 0.7 V; see Figure 3.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
5
5 Page 
www.DDatDaSRh2eeSt4DUR.cAomM
Table 15 provides the current draw characteristics for MVREF.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition
Symbol
Min
Max
Current draw for MVREF
IMVREF
—
500
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 μA current.
Unit
μA
Note
1
6.2 DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1 DDR2 SDRAM Input AC Timing Specifications
Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8V.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface
At recommended operating conditions with GVDD of 1.8 ± 100 mV
Parameter
Symbol
Min
Max
Unit Notes
AC input low voltage
AC input high voltage
VIL — MVREF – 0.45 V —
VIH MVREF + 0.45
—
V—
Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 17. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 1.8± 100 mV
Parameter
Symbol
Min
Max
Unit Notes
Controller skew for MDQS—MDQ/MECC @266 MHz tCISKEW
–875
875
ps 1, 2,3
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called tDISKEW. This can
be determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is
the absolute value of tCISKEW.
3. Memory controller ODT value of 150 Ω is recommended
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC8308.PDF ] | |
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