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BU7964GUW 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BU7964GUW은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 BU7964GUW 기능
기능 Data rate 1350Mbps RGB Interface
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BU7964GUW 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones
Data rate 1350Mbps
RGB Interface
BU7964GUW
No.10058EAT04
Description
BU7964GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is
utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration
in hinge phones - resulting in greater reliability and design flexibility.
Features
1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps.
2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface.
3) Pixel clock frequency range from 4 to 45MHz.
4) Depending on the data transfer rate, either, two or three differential data channels can be selected.
Applications
Serial Interface for LCD Display Interface of Mobile Devices Application.
Absolute Maximum Ratings
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Input Current
Output Current
Preservation Temperature
Symbol
DVDD
MSVDD
VIN
VOUT
IIN
IOUT
Tstg
Ratings
-0.3 ~ +2.5
-0.3 ~ +2.5
-0.3 ~ MSVDD+0.3
-0.3 ~ DVDD+0.3
-0.3 ~ MSVDD+0.3
-0.3 ~ DVDD+0.3
-10 ~ +10
-70 ~ +70
-55 ~ +125
Unit Remarks
V-
V-
V I/O terminals of MSVDD line
V I/O terminals of DVDD line
V I/O terminals of MSVDD line
V I/O terminals of DVDD line
mA -
mA -
-
Operating Conditions
Parameter
Supply Voltage for DVDD
Supply Voltage for MSVDD
Data Transmission Rate
Operating Temperature Range
Symbol
VDVDD
VMSVDD
DR
Topr
Min
1.65
1.65
120
-30
Ratings
Typ
1.80
1.80
-
25
Max
1.95
1.95
450
85
Unit Conditions
V
V
Mbps/ch
VDVDD = VMSVDD
-
-
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.04 - Rev.A




BU7964GUW pdf, 반도체, 판매, 대치품
BU7964GUW
Pin Layout
Technical Note
www.DataSheet4U.com
12345678
A TEST0 PD19
PD17
PD16
PD14
PD13
PD10
CPO
B
PCLK
PD18
PD15
PD12
PD11
PD9
PD8
C PD22 PD20 PLL_BW0 DVDD N.C.
F_XS
PD7
PD6
D PD23 PD21
N.C.
DGND
DGND
DVDD
PD4
PD5
E
PD25
PD24
DVDD
DGND MSGND
N.C.
PD1
PD3
F PD26
LS0 MSVDD MSGND MSVDD N.C.
XSD
PD2
G LS1 PLL_BW1 D2-
D1- CLK- D0- N.C. PD0
H N.C.
N.C.
D2+
D1+
CLK+
D0+
DRVR
TEST1
Fig.3. Pin Layout (Top View)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
4/18
2010.04 - Rev.A

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BU7964GUW 전자부품, 판매, 대치품
BU7964GUW
Technical Note
www.DataSheet4U.com
Operation Control
MSDL3 Channel Count Selection
Pins LS0 and LS1 are used to control the high-speed data channel count and data format. High-speed data channel count,
data format should be the same between the transmitting and receiving devices (the BU7963GUW and BU7964GUW,
respectively). Table 6 shows and Receipt Data rate ranges for the LS pin settings.
LS1 LS0
‘L’ ‘L’
‘L’ ‘H’
‘H’ ‘L’
Table 6. The Range of The Receipt Data rate
The Number of Data Channel
The Range of PCLK Input
Frequency [MHz]
1-channel (27-bit format).
4.0-15.0
2-channel (27-bit format).
8.0-30.0
3-channel (27-bit format).
12.0-45.0
The Range of
The Data Receipt Rate
[Mbits/sec]
120-450
240-900
360-1350
CMOS Output Drivability Selection
F_XS determines output drivability of the parallel data interface. Table 7 shows output drivability.
F_XS
Table 7. Output Drivability
Output Drivability
‘L’ 1mA Type
‘H’ 3mA Type
PLL Bandwidth Selection
BU7964GUW controls the range of the CLK+ / CLKinput frequency (= PCLK output frequency) by the setting of the
data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW0 and PLL_BW1.
Table 8. PLL Bandwidth Selection
CLK+/CLK- Frequency Range [MHz]
LS1
LS0
PLL_BW1
PLL_BW0
(PCLK Input Frequency)
Min Max
‘L’ ‘L’ ‘L’ ‘L’ 4
7
‘L’ ‘L’ ‘L’ ‘H’ 6 11
‘L’ ‘L’ ‘H’ ‘L’ 10 15
‘L’ ‘H’ ‘L’ ‘L’ 8 14
‘L’ ‘H’ ‘L’ ‘H’ 12 22
‘L’ ‘H’ ‘H’ ‘L’ 20 30
‘H’ ‘L’ ‘L’ ‘L’ 12 21
‘H’ ‘L’ ‘L’ ‘H’ 18 33
‘H’ ‘L’ ‘H’ ‘L’ 30 45
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
7/18
2010.04 - Rev.A

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