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PDF BU7988KVT Data sheet ( Hoja de datos )

Número de pieza BU7988KVT
Descripción 56bit LVDS Transmitter 56:8 Serializer
Fabricantes ROHM Semiconductor　
Logotipo ROHM Semiconductor Logotipo



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No Preview Available ! BU7988KVT Hoja de datos, Descripción, Manual

LVDS Interface ICs
56bit LVDS Transmitter
56:8 Serializer
BU7988KVT
No.12057EAT05
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits
range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The
ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
1) Wide dot clock range : Single(112MHz)/Dual(224MHz)(NTSC, VGA, SVGA, WXGA UXGA)
2) Support spread spectrum clock generator.
3) Clock edge selectable.
4) Support reduced swing LVDS for low EMI.
5) Power down mode.
6) Package TQFP100V
●Applications
Flat Plane Display
●Precaution
■This chip is not designed to protect from radioactivity.
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
1/27
2011.12 - Rev.A

1 page




BU7988KVT pdf
BU7988KVT
Technical Note
●Pin Description
Table 1 : Pin Description
Pin Name
Pin No.
Type
Descriptions
TA1P, TA1N
48, 49
TB1P, TB1N
46, 47
TC1P, TC1N
43, 44
TD1P, TD1N
39, 40
TCLK1P, TCLK1N
41, 42
TA2P, TA2N
36, 37
TB2P, TB2N
34, 35
TC2P TC2N
31, 32
TD2P, TD2N
27, 28
TCLK2P, TCLK2N
29, 30
R17～R10
60, 59, 58, 57, 54, 53, 52, 51
G17～G10
68, 67, 66, 65, 64, 63, 62, 61
B17～B10
78, 77, 76, 75, 74, 73, 70, 69
R27～R20
86, 85, 84, 83, 82, 81, 80, 79
G27～G20
96, 95, 94, 93, 92, 91, 90, 89
B27～B20
6, 5, 2, 1, 100, 99, 98, 97
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
IN
IN
IN
IN
IN
IN
LVDS data out
LVDS clock out
LVDS data out
LVDS clock out
1ｓｔ Pixel data input.
2ｓｔ Pixel data inputs.
DE 9 IN DATA-ENABLE input.
VSYNC
8
IN VSYNC input.
HSYNC
7
IN HSYNC input.
CLKIN 10 IN Clock Input.
MAP
LVDS mapping table select.
14 IN See Table11-14 and Figure11-14.
XRST
19
IN
H : Normal operation,
L : Power down (all outputs are Hi-Z)
FLIP 21 IN LVDS output pin select. See Table10.
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
5/27
2011.12 - Rev.A

5 Page





BU7988KVT arduino
BU7988KVT
Technical Note
■AC characteristics
Table 8 : Switching Characteristics (VDD=3.3V, Ta=25℃)
Parameter
Symbol
CLK IN Transition time
Dual In /Dual Out
tTCIT
CLK IN Period
Dual In / Single Out
Single In / Dual Out
tTCP
Single In / Single Out
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/-Delay
Dual In /Dual Out
Single In/Single Out
Dual In / Single Out
Single In / Dual Out
tTCH
tTCL
tTCD
CMOS Data Setup to CLK IN
CMOS Data Hold from CLK IN
Dual In /Dual Out
tTS
tTH
CLK OUT Period
Dual In / Single Out
Single In / Dual Out
tTCOP
Single In / Single Out
LVDS Transition Time
Output Data Position 0
tLVT
tTOP1
Output Data Position 1
tTOP0
Output Data Position 2
tTOP6
Output Data Position 3
tTOP5
Output Data Position 4
tTOP4
Output Data Position 5
tTOP3
Output Data Position 6
tTOP2
Skew Time between TCLKXP and TCLKYP
Phase Lock Loop Set Time
Tck12
tTPLL
Min
-
8.9
17.8
6.7
8.9
0.35tTCP
0.35tTCP
-
-
-
2.5
0
8.9
8.9
13.3
8.9
-
-0.2
tTCP
-0.2
7
tTCP
2 -0.2
7
tTCP
3 7 -0.2
tTCP
4 7 -0.2
tTCP
5 7 -0.2
tTCP
6 7 -0.2
-
-
Typ
-
-
-
-
0.5tTCP
0.5tTCP
TBD
TBD
TBD
-
-
-
-
-
0.6
0.0
tTCP
7
tTCP
2
7
tTCP
37
tTCP
47
tTCP
57
tTCP
67
-
-
Max Units
5.0 ns
125.0
ns
62.5
250.0
125.0
0.65tTCP
ns
0.65tTCP
ns
- ns
-
-
- ns
- ns
125.0
125.0
125.0
125.0
1.5 ns
+0.2
tTCP
+0.2
7
tTCP
2 +0.2
7
tTCP
3 7 +0.2
tTCP
4 7 +0.2
tTCP
5 7 +0.2
tTCP
6 7 +0.2
0.5
ns
ns
ns
ns
ns
ns
ns
ns
10.0 ms
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
11/27
2011.12 - Rev.A

11 Page







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