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0N05HDL 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP60N05HDL/D
www.DataSheet4U.com
Product Preview
HDTMOS E-FET .
Power Field Effect Transistor
MTP60N05HDL
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
TMOS POWER FET
60 AMPERES
50 VOLTS
RDS(on) = 0.014 OHM
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D
G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp 10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
50 Vdc
50 Vdc
± 15 Vdc
± 20 Vpk
60 Adc
42
180 Apk
150 Watts
1.0 W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
— Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 5 Seconds
TJ, Tstg
EAS
RθJC
RθJA
TL
– 55 to 175
540
1.0
62.5
260
°C
mJ
°C/W
°C
E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1




0N05HDL pdf, 반도체, 판매, 대치품
MTP60N05HDL
POWER MOSFET SWITCHING
www.DataSheet4U.com
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
10,000
9000
Ciss
8000
VDS = 0 VGS = 0
TJ = 25°C
7000
6000 Crss
5000
4000
3000
Ciss
2000
Coss
1000 Crss
0
–10 –5.0
0
5.0 10 15 20
25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

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0N05HDL 전자부품, 판매, 대치품
1.0
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
SINGLE PULSE
0.01
0.00001
0.0001
MTP60N05HDL
www.DataSheet4U.com
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
0.001
0.01
t, TIME (s)
0.1
Figure 14. Thermal Response
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0 10
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7

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