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PDF BR24C21F Data sheet ( Hoja de datos )
| Número de pieza | BR24C21F | |
| Descripción | EDID Memory (For display) | |
| Fabricantes | ROHM Semiconductor | |
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www.DataSheet4U.com
Memory for Plug & Play
EDID Memory
(For display)
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
No.09002EAT02
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV
●Description
BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1TM/DDC2TM interfaces
for Plug and Play displays.
●Features
1) Compatible with both DDC1TM/DDC2TM
2) Operating voltage range: 2.5V to 5.5V
3) Page write function: 8bytes
4) Low power consumption
Active (at 5V) : 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
5) Address auto increment function during Read operation
6) Data security
Write enable feature (VCLK)
Write protection at low Vcc
7) Various packages available: DIP-T8(BR24C21) / SOP8(BR24C21F) / SOP-J8(BR24C21FJ) / SSOP-B8(BR24C21FV)
8) Initial data=FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Rating
Supply Voltage
VCC -0.3～+6.5
800 (DIP-T8)
*1
Power Dissipation
Pd
450 (SOP8)
450 (SOP-J8)
*2
*3
350 (SSOP-B8) *4
Storage Temperature
Tstg -65～+125
Operating Temperature
Topr
-40～+85
Terminal Voltage
- -0.3～VCC+0.3
* Reduce by 8.0 mW/C over 25C (*1), 4.5mW/℃ (*2,3), and 3.5mW/℃ (*4)
Unit
V
mW
℃
℃
V
●Memory cell characteristics
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
VIN
Rating
2.5～5.5
0～VCC
Unit
V
V
●Recommended operating conditions
Parameter
Write/Erase Cycle
Data Retention
Min.
100,000
10
Limits
Typ.
-
-
Max.
-
-
Unit
Cycle
Year
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/22
2009.04 - Rev.A
1 page  
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
www.DataSheet4U.com
●Bi-directional mode
○Bi-directional Mode and Recovery Function
・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low
transition at the SCL pin, while the state of SDA is at high-impedance.
・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK
counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode
(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal
to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.
・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional
Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only
way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an
Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for
Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,
it is possible to revert to Transmit-Only Mode.
・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.
ＭＯＤＥ TTrarnasmnits-monli yt - o n l y
B i - dBii-rdeircecttiioonnaal l
T r aTnrasnistiitioonn MModeo dwieth wpoistshibipliotys stoi b i l i t y
t o rreettuurnnteo TtroansTmirta-OnnslymMiotd-eO n l y M o d e
T r a nTrsanmsmiti -tO-nlOy n l y
ＶＣＬＫ
ＳＣＬ
ＳＤＡ
１２３４
１２７ １２８ １２９
ｔＶＨＺ
A D DADRDREESSSS 000h0 h
Ｄ７ Ｄ６ Ｄ５ Ｄ４
Fig.8 Recovery Mode
TTrarnasmint-soOmnlyi t - o n l y
ＭＯＤＥ
BBii--ddirierceticontailo n a l
TTrraansnitsiiotni oMonde Mwiothdpeosswibiitlhityptoos s i b i l i t y
troeturren ttuo nTreanstmoit-TOrnlaynMsodme i t - O n l y M o d e
ＶＣＬＫ
１２
ｎ＜１２８
ｎ
B i - d i rBie-cditrieoctnioanal l
p a r m paanrmeannent tl lyy
ＳＣＬ
ＳＤＡ
ｔＶＨＺ
Ｓ １ ０ １ ０ ＊ ＊ ＊ Ｒ/Ｗ ＡＣＫ
Fig.9 Mode Change
*Don’t care
○Bi-directional Mode
START Condition
・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.
・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to
any commands until this condition has been met.
(See Fig. 3 Synchronous Data Timing)
STOP Condition
・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.
・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.
・The STOP condition is also used to place the device into standby power mode after read sequences.
・A STOP condition can only be issued after the transmitting device has released the bus.
(See Fig.3 Synchronous Data Timing)
Device Addressing
・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most
significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as
“1010.”
・The next three bits of the slave address are inconsequential.
・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.
When set to “0”, a WRITE operation is initiated.
R/W set to "0" ・ ・ ・ ・ ・ ・ ・ ・ WRITE (This bit is also set to "0" for random read operation)
R/W set to "1" ・ ・ ・ ・ ・ ・ ・ ・ READ
1010
＊＊＊
_
R/W
＊：Don’t care
○Write Protect Function
・Write Enable (VCLK)
When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting
VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.
(See Fig.5 Write Enable Timing)
Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/22
2009.04 - Rev.A
5 Page 
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
●Synchronous data timing
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tR tF
tHIGH
tSU:DAT tLOW
tPD
tHD:DAT
SCL
tSU:STA
SDA
Fig.17 Synchronous Data Timing
・SDA data is latched into the chip at the rising edge of the SCL clock.
・The output date toggles at the falling edge of the SCL clock.
●Write cycle timing
SCL
tHD:STA
START BIT
Technical Note
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tSU:STO
STOP BIT
SDA
D0
WRITE DATA (n)
ACK
tWR
STOP CONDITION
START CONDITION
Fig.18 Write Cycle Timing
●Operation notes
○DDCENA Operation
When DDCENA is set to High, SCL_PC0/1 and SDA_PC0/1 will be connected to SCL_MON and SDA_MON,
respectively. Therefore, monitoring of the communications between the PC and EEPROM, and the communications of
the MONITOR and PC, is possible.
Selection of PC0/PC1 is determined according to the state of the DUALPCB and BANKSEL inputs.
When DDCENA is Low, the SCL/SDA_MON output is set to "Hi-Z".
DUALPCB
BANKSEL
SCL_MON,SDA_MON
(CONNECTION PORT)
Low (DUAL PORT)
Low
High
PC0 PORT
PC1 PORT
High (SINGLE PORT)
Low
High
PC0 PORT
○BANKSEL
BANKSEL serves as an input for connection port of SCL/SDA_MON during DUAL PORT mode.
It turns into the BANK selection terminal of internal memory in SINGLE PORT mode.
Only the PC0 port can access the memory in SINGLE PORT mode.
DUALPCB
Low (DUAL PORT)
High (SINGL PORT)
BANKSEL
Low
High
Low
High
CONNECTION BANK
PC0 PORT：BANK0
PC1 PORT：BANK1
BANK0
BANK1
○WP
When WP=Low, all data at all addresses are write-protected. The terminal has a built-in pull down resister. Make sure
that WP=High when writing data.
Utilize this function in order to prevent incorrect write command input from the PC, as well as incorrect input during
communication between the PC and monitor.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/22
2009.04 - Rev.A
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet BR24C21F.PDF ] | |
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