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BR24C21FJ 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BR24C21FJ은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 BR24C21FJ 자료 제공

부품번호 BR24C21FJ 기능
기능 EDID Memory (For display)
제조업체 ROHM Semiconductor
로고 ROHM Semiconductor 로고


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BR24C21FJ 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Memory for Plug & Play
EDID Memory
(For display)
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
No.09002EAT02
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV
Description
BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1TM/DDC2TM interfaces
for Plug and Play displays.
Features
1) Compatible with both DDC1TM/DDC2TM
2) Operating voltage range: 2.5V to 5.5V
3) Page write function: 8bytes
4) Low power consumption
Active (at 5V) : 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
5) Address auto increment function during Read operation
6) Data security
Write enable feature (VCLK)
Write protection at low Vcc
7) Various packages available: DIP-T8(BR24C21) / SOP8(BR24C21F) / SOP-J8(BR24C21FJ) / SSOP-B8(BR24C21FV)
8) Initial data=FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
Absolute maximum ratings (Ta=25)
Parameter
Symbol
Rating
Supply Voltage
VCC -0.3+6.5
800 (DIP-T8)
*1
Power Dissipation
Pd
450 (SOP8)
450 (SOP-J8)
*2
*3
350 (SSOP-B8) *4
Storage Temperature
Tstg -65+125
Operating Temperature
Topr
-40+85
Terminal Voltage
- -0.3VCC+0.3
* Reduce by 8.0 mW/C over 25C (*1), 4.5mW/(*2,3), and 3.5mW/(*4)
Unit
V
mW
V
Memory cell characteristics
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
VIN
Rating
2.55.5
0VCC
Unit
V
V
Recommended operating conditions
Parameter
Write/Erase Cycle
Data Retention
Min.
100,000
10
Limits
Typ.
-
-
Max.
-
-
Unit
Cycle
Year
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/22
2009.04 - Rev.A




BR24C21FJ pdf, 반도체, 판매, 대치품
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Synchronous data timing
tR tF
t HI GH
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tSU:DAT
tLOW
tPD
tHD:DAT
Technical Note
www.DataSheet4U.com
SCL
SDA
D0 ACK
WRITE DATA(n)
tWR
STOP CONDITION START CONDITION
Fig.4 Write Cycle Timing
START BIT STOP BIT
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
Fig.3 Synchronous Data Timing
SCL
SDA
STOP BIT
VCLK
SDA data is latched into the chip at the rising edge of the SCL clock.
Output data toggles at the falling edge of the SCL clock.
tVSU WRITE COMMAND tVHD
Fig.5 Write Enable Timing
Transmit-only mode
After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock
to the VCLK pin.
When the power is on, the SCL pin needs to be set to VCC(High level).
SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After
power on, the output data is as follows:
00h address data 01h address data 02h address data
The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)
In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)
The read operation is in Transmit-Only Mode and can be started after the power is stabilized.
Vcc
SCL
VCLK
tVPU
SDA
1 9 10
D7 D6 D5 D4 D3
00h ADDRESS DATA
Fig.6 Transmit Only Mode
VCLK
SDA
tVPD
D1
ADDRESS n
DATA
tVHIGH tVLOW
D0 D7 D6
NULL BIT
DATA=1
ADDRESS n+1
DATA
Fig.7 Null Bit
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
4/22
2009.04 - Rev.A

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BR24C21FJ 전자부품, 판매, 대치품
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
www.DataSheet4U.com
Random Read
The Random read operation allows the Master to access any memory location. This operation involves a two-step
process. First, the Master issues a Write command that includes the START condition and the Slave address field
(with R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address
counter of the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the
Master, the Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.”
The device will respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the
Master does not acknowledge the transmission but does generate the STOP condition, the IC will discontinue
transmission.
SDA
LINE
SW
TR
AI
R SLAVE T
T ADDRESS E
WORD
ADDRESS(n)
S
TR
AE
R SLAVE A
T ADDRESS D
DATA(n)
S
T
O
P
1010***
*
WA
6
RA
/C
WK
WA
0
1010***
D7
A RA
C /C
K WK
D0
A
C
K
*:Dont care
Fig.13 Random Read Cycle Timing
Sequential Read
If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits
in the address counter are incremented, allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.
If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device
discontinues transmission.
The sequential Read operation can be performed with both Current Read and Random Read.
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
1010***
D7
D0
DATA(n+x)
S
T
O
P
D7 D0
RA A A A
/C C C C
W K K K *:Dont care K
Fig.14 Sequential Read Cycle Timing
(Current Read)
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
7/22
2009.04 - Rev.A

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관련 데이터시트

부품번호상세설명 및 기능제조사
BR24C21F

ID ROM for CRT display

ROHM Semiconductor
ROHM Semiconductor
BR24C21F

EDID Memory (For display)

ROHM Semiconductor
ROHM Semiconductor

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