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PDF BU9883FV-W Data sheet ( Hoja de datos )
| Número de pieza | BU9883FV-W | |
| Descripción | I2C BUS3Ports for HDMI Port Serial EEPROM | |
| Fabricantes | ROHM Semiconductor | |
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Memory for Plug & Play
I2C BUS3Ports for HDMI Port
Serial EEPROM
BU9883FV-W
No.09002EBT01
● Description
BU9883FV-W is for DDC 3 ports, 2K x 8 bit array 3 BANK EEPROM.
●Features
1) There are 3 BANKs, 1 BANK compose of 256 word address x 8 bit EEPROM
2) There are 3 DDC interface channels, and each channel can access each BANK independently from other ports.
3) 2K bit X 3 BANK memory bits can be accessed from write port (Port0).
4) Operate voltage (3.0V～5.5V)
5) Built in diode for power supply from HDMI ports and system.
6) Automatic erase
7) 8 byte page write mode
8) Low power consumption
Active ( 5.0V ) : 1.2mA (Typ.)
Standby ( 5.0V ) : 100μA(Max.)
9) DATA security
10) Write Protect pin can switch write port
11) Inhibit to WRITE at low VCC
12) Pin package
: SSOP16pin
13) Endurance
: 1,000,000 erase/write cycles
14) Data retention
40 years
15) Filtered inputs in all SCL・SDA for noise suppression
16) Shipment data all address FFh
●Absolute maximum rating (Ta=25℃)
Parameter
Symbol
Supply Voltage
VCC
Power Dissipation
Pd
Storage Temperature
Tstg
Operating Temperature
Topr
Terminal Voltage
-
*1 Degradation is done at 3.0mW/℃ for operation above 25℃
*2 The Max value of terminal voltage is not over 6.5V
Rating
-0.3～6.5
400 *1
-65 ～ 125
-40 ～ 85
-0.3～VCC＋0.3
*1
Unit
V
mW
℃
℃
V
●EEPROM recommended operating condition
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
VIN
Rating
3.0～5.5
0 ～ VCC0～3
Unit
V
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/18
2009.04 - Rev.B
1 page  
BU9883FV-W
●Characteristic data (The following values are Typ. ones).
300
250
Ta=-40℃
Ta=25℃
200 Ta=85℃
150 SPEC
100
50
0
0123456
SUPPLY VOLTAGE : Vcc2[V]
Fig.23 Standby Current2 ISB2
300
250
Ta=-40℃
Ta=25℃
200 Ta=85℃
150
SPEC
100
50
0
0123456
SUPPLY VOLTAGE : Vcc3[V]
Fig.24 Standby Current ISB3
800
700
600
500
400
300
200
100
0
0
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
12345
SUPPLY VOLTAGE : Vcc[V]
6
Fig.26 Data Clock Hｉｇｈ Period tHIGH
1400
1200
1000 SPEC
800
600
400
Ta=-40℃
Ta=25℃
200 Ta=85℃
0
0123456
SUPPLY VOLTAGE : Vcc[V]
Fig.27 Data Clock Low Period tLOW
800
600
Ta=-40℃
400
Ta=25℃
Ta=85℃
200
SPEC
0
0
1000
12345
SUPPLY VOLTAGE : Vcc[V]
Fig.29 Start Condition Setup
Time tSU:STA
Ta=-40℃
800 Ta=25℃
Ta=85℃
600
SPEC
6
400
200
0
0123456
SUPPLY VOLTAGE : Vcc[V]
Fig.32 Output Data Delay Time ｔPD
400
Ta=-40℃
300 Ta=25℃
Ta=85℃
200
100
0
0
SPEC
12345
SUPPLYVOLTAGE : Vcc[V]
Fig.35 Noise Spike Width tI
(SDA0～3 and SCL0～3)
6
20
0
-20
Ta=-40℃
-40 Ta=25℃
Ta=85℃
-60
SPEC
-80
0
123456
SUPPLY VOLTAGE : Vcc[V]
Fig.30 Input Data Hold Time tHD：DAT
800
Ta=-40℃
600 Ta=25℃
Ta=85℃
400
SPEC
200
0
-200
0
12345
SUPPLYVOLTAGE : Vcc[V]
6
Fig.33 Stop Condition Setup Time tSU：STO
200
Ta=-40℃
100 Ta=25℃
Ta=85℃
0
SPEC
-100
-200
-300
0
12345
SUPPLYVOLTAGE : Vcc[V]
Fig.36 WP Setup Time tSU:WP
6
Technical Note
www.DataSheet4U.com
1000
Ta=-40℃
800 Ta=25℃
Ta=85℃
600
400
SPEC
200
0
0123456
SUPPLY VOLTAGE : Vcc[V]
Fig.25 Clock Frequency fSCL
800
Ta=-40℃
600 Ta=25℃
Ta=85℃
400
SPEC
200
0
0123456
SUPPLY VOLTAGE : Vcc[V]
Fig.28 Sｔａｒｔ Condition Hold Time ｔHD:STA
120
SPEC
100
80
60
Ta=-40℃
40 Ta=25℃
Ta=85℃
20
0
0123456
SUPPLY VOLATGE : Vcc[V]
Fig.31 Input Data Setup Time ｔSU:DAT
6
Ta=-40℃
5 Ta=25℃
Ta=85℃
4
SPEC
3
2
1
0
0123456
SUPPLYVOLTAGE : Vcc[V]
Fig.34 Write Cycle Time tWR
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/18
2009.04 - Rev.B
5 Page 
BU9883FV-W
Technical Note
www.DataSheet4U.com
○When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including
Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output.
When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
○Current Read operation allows the master to access data word stored in internal address counter which is appointed by
P1, P0 bit. This operation involves a two-step process. This device will respond with an acknowledge and then transmit
the 8-data bits stored at the addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
note)If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address
data, and master can't send stop condition, so master can't discontinues transmission.
To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.
S
TR
AE
R
T
SLAVE
A
ADDRESS D
DATA(n)
SDA
LIN
1 0 1 0 0 P1 P0
D7
D0
D AT A(n +x）
S
T
O
P
D7 D0
WPB
Fig.46 SEQUENTIAL READ CYCLE TIMING （PORT0）
○During the sequential read operation, the internal address counter of this device automatically increments with each
acknowledge received ensuring the data from address will be followed with the data from n+1. For read operations, all bits
of the address counter are incremented allowing the entire array to be read during a single operation. When the counter
reaches the top of the array, it will “roll over” to the bottom of the array of BANK and continue to transmit the data.
○The sequential read operation can be performed with both current read and random read.
●PORT1,2,3 access commands
SDA
LINE
SW
TR
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS(n)
S
TR
A
R
T
SLAVE
ADDRESS
E
A
D
1010 00 0
WA7
RA
/C
WK
WA0
A
C
K
1010 00 0
D7
RA
/C
WK
DATA(n)
S
T
O
P
D0
A
C
K
WPB
Fig.47 RANDOM READ CYCLE TIMING（PORT1～3）
○Random read operation allows the master to access any memory location of the BANK which is appointed by P1, P0. This
operation involves a two-step process.
First, the master issues a write command which includes the start condition and the slave address field (with R/W set to
“0”) followed by the address of the word be read.
This procedure sets the internal address counter of this device to the desired address.
After the word address acknowledge is received by the master, the master immediately reissues a start condition followed
by the slave address field with R/W the set to “1.”
This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the
master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues
transmission.
S
TR
A
R
T
SLAVE
ADDRESS
E
A
D
DATA
S
T
O
P
SDA
LINE
1 0 1 0 0 00
D7
D0
WPB
RA
/C
WK
A
C
K
Fig.48 CURRENT READ CYCLE TIMING（PORT1～3）
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/18
2009.04 - Rev.B
11 Page | ||
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| PDF Descargar | [ Datasheet BU9883FV-W.PDF ] | |
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