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부품번호 BU9889GUL-W
기능 WL-CSP EEPROM family I2C BUS
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BU9889GUL-W 데이터시트, 핀배열, 회로
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High Reliability Series Serial EEPROM Series
WL-CSP EEPROM family
I2C BUS
BU9889GUL-W
Description
BU9889GUL-W is a serial EEPROM of I2C BUS interface method.
Features
1) Completely conforming to the world standard I2C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) 1k words×8 bits architecture 8kbit serial EEPROM.
3) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
4) 1.75.5V single power source action most suitable for battery use.
5) FAST MODE 400kHz at 1.75.5V
6) Page write mode useful for initial value write at factory shipment.
7) Auto erase and auto end function at data rewrite.
8) Low current consumption
At write operation (5V)
: 0.5mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1µA (Typ.)
9) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
10) WLCSP6pin compact package
11) Data rewrite up to 100,000 times
12) Data kept for 40 years
13) Noise filter built in SCL / SDA terminal
14) Shipment data all address FFh
Absolute maximum ratings (Ta=25)
Parameter
symbol
Limits
Impressed voltage
Permissible dissipation
VCC -0.3+6.5
Pd 220*1
Storage temperature range
Tstg -65+125
Action temperature range
Topr -40+85
Terminal voltage
- -0.3Vcc+1.0
*1 When using at Ta=25or higher, 2.2mW to be reduced per 1
Unit
V
mW
V
Memory cell characteristics (Ta=25, Vcc=1.75.5V)
Parameter
Limits
Min. Typ.
Number of data rewrite times *1
100,000
-
Data hold years *1
40 -
*1 Not 100% TESTED
Max.
-
-
Unit
Times
Years
Recommended operating conditions
Parameter
Symbol
Power source voltage
Vcc
Input voltage
VIN
Limits
1.75.5
0Vcc
Unit
V
No.10001EAT07
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/17
2010.01 - Rev.A




BU9889GUL-W pdf, 반도체, 판매, 대치품
BU9889GUL-W
Block diagram
A2
Technical Note
www.DataSheet4U.com
8Kbit EEPROM ARRAY
10bit
ADDRESS
DECODER
10bit
SLAVE、WORD
ADDRESS REGISTER
8bit
DATA
REGISTER
Vcc
GND
WP
START
CONTROL LOGIC
STOP
ACK
HIGH VOLTAGE GEN.
Vcc LEVEL DETECT
SCL
SDA
Pin assignment and description
○ ○B B1 B2 B3
SDA GND A2
A A1 A2 A3
SCL WP VCC
1 23
BU9889GUL-W (BOTTOM VIEW)
Fig.2 Block diagram
Terminal
name
A2
GND
SDA
SCL
WP
Vcc
Input/
Output
Input
-
Input /
Output
Input
Input
-
Function
Slave address setting
Reference voltage of all input / output, 0V.
Slave and word address,
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
Characteristic data (The following values are Typ. ones.)
66
5
Ta=-40℃
Ta=25℃
Ta=85℃
4
5 Ta=-40℃
Ta=25℃
4 Ta=85℃
3
SPEC
2
3
2
1
0
012345
SUPPLY VOLTAGE : Vcc(V)
FFigi.g3. 3 'H'Hin' pinuptuvtovltoalgtaeg eVVIHIH
(A2(A,S2C,SLC,SLD,SAD,WA,PW)P)
1
0.8
0.6 Ta=-40℃
Ta=25℃
Ta=85℃
0.4
SPEC
0.2
6
1
0
0
1.2
1
SPEC
12345
SUPPLY VOLTAGE : Vcc(V)
FFigi.g4.4 'L''Lin' pinuptuvtovltoalgtaeg eVVILIL
(A2(A,S2C,SLC,SLD,SAD,WA,PW)P)
SPEC
0.8
0.6
Ta=-40℃
0.4 Ta=25℃
Ta=85℃
0.2
6
0
0123456
L OUTPUT CURRENT : IOL(mA)
FFigig.6.6 'L' oouuttppuutt vvoollttaaggeeVVOOLL--IOIOLL(Vcc=2.5V)
0
0123456
SUPPLYVOLTAGE : Vcc(V)
FigF.i7g.7 InInppuut tleleaakkccuurrrerennt LtII ILI
(A(A2,2S,SCCL,LW,WP)P)
1
Ta=-40℃
0.8 Ta=25℃
Ta=85℃
0.6
0.4
SPEC
0.2
0
01234567
L OUTPUT CURRENT : IOL(mA)
FigF.5ig.5'L' ('oVLu'ctocpu=ut1tp.vu7otVlvt)aoglteagVeOLV-OL- IOL
I (V 1 7V)
1.2
SPEC
1
8
0.8
0.6
0.4 Ta=-40℃
Ta=25℃
0.2 Ta=85℃
0
0123456
SUPPLY VOLTAGE : Vcc(V)
FigF.8ig.8O OutuptuptultelaekakcucrurerrnetnItLO (SDA)
I (SDA)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
4/17
2010.01 - Rev.A

4페이지










BU9889GUL-W 전자부품, 판매, 대치품
BU9889GUL-W
Technical Note
www.DataSheet4U.com
I2C BUS communication
I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7 8 9
1-7 8 9
1-7 8
SCL
S
START ADDRESS
condition
R/W ACK
DATA
ACK
Fig.31 Data transfer timing
DATA
9
P
ACK STOP
condition
Start condition (start bit recognition)
Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
Stop condition (stop bit recognition)
Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
Acknowledge (ACK) signal
This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of
read command) at the transmitter (sending) side releases the bus after output of 8bit data.
The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
Device addressing
Following a START condition, the master output the slave address to be accessed.
The most significant four bits of the slave address are the “device type indentifier,” for this device it is fixed as “1010”.
The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2
input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin.
Using this address scheme, up to two devices may be connected to the bus.
The next two bits (P1, P0) are used by the master to select four 256 word page of memory.
P1, P0 set to “0” “0” ・・・ 1page (0000FF)
P1, P0 set to “0” “1” ・・・ 1page (1001FF)
P1, P0 set to “1” “0” ・・・ 1page (2002FF)
P1, P0 set to “1” “1” ・・・ 1page (3003FF)
The last bit of the stream (R/W READ/WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R/W set to “0” ・・・ WRITE (including word address input of Random Read)
R/W set to “1” ・・・ READ
1010
A2
P1
P0 R/W
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
7/17
2010.01 - Rev.A

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BU9889GUL-W

WL-CSP EEPROM family I2C BUS

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