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PDF BU6521KV Data sheet ( Hoja de datos )
| Número de pieza | BU6521KV | |
| Descripción | Video Encoders built-in Image Correction | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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AIE Adaptive Image Enhancer Series
Video Encoders
built-in Image Correction
BU6520KV,BU6521KV
No.10060ECT03
●Description
BU6520KV, BU6521KV are video encoders with built-in AIE image correcting function. Also, BU6521KV has the image
correcting function of the fog reduction, too.
Fog Reduction, the brightness correction, the backlight correction and the chroma emphasis can improve the visibility of the
input image of the camera.
* AIE and Fog Reduction function are image processing technology by ROHM’s hardware.
●Features
1) Format of video output is compatible with NTSC/PAL composite video format (CVBS).
Built-in DAC with direct 75Ω drive capability.
2) Built-in Fog Reduction function*1, dynamic range correction, edge-emphasizing filter and gamma filter.
3) Input/output data format is compatible with ITU-R BT.656 and YCbCr=4:2:2 with synchronization signal.
4) Compatible with NTSC (27MHz, 28.63636MHz and 19.06993MHz)/
PAL(27MHz, 28.375MHz, 35.46895MHz and 18.9375MHz) *2.
5) Registers can be set up with a 2-line serial interface.
6) Registers can be automatically set up by reading from external EEPROM, when after resetting or changing mode.
*1 As for the Fog Reduction feature, it loads only BU6521KV.
*2 NTSC 19,06993 MHz and PAL 18,9375 MHz support only BU6521KV.
●Applications
Security camera, camera for automotive, drive recorder etc.
●Line up matrix
Part No.
Power Sopply
Voltage(V)
Image size
Input
Interface
Control
Interface
Output
Interface
Feature
Temperature
Operating Package
Range(℃)
1.4 to 1.6
BU6520KV
(VDDCore)
2.7 to 3.6
(VDDI/O, AVDD)
720x480,
SD size
8bit,
YUV=4:2:2,
ITU-R BT.656
I2C,
Serial
EEPROM
interface
8bit,
YUV=4:2:2,
ITU-R BT.656
AIE,
Video output
-40 ~ +85 VQFP48C
1.4 to 1.6
BU6521KV
(VDDCore)
2.7 to 3.6
(VDDI/O, AVDD)
720x480,
SD size
8bit,
YUV=4:2:2,
ITU-R BT.656
I2C,
Serial
EEPROM
interface
8bit,
YUV=4:2:2,
ITU-R BT.656
AIE,
Fog reduction,
Video output
-40 ~ +85
VQFP48C
I2C BUS is a registered trademark of Philips
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.02 - Rev.C
1 page  
BU6520KV,BU6521KV
Technical Note
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PIN
No.
PIN Name
In/Out
Active
Level
Init
Function explanation
25 CAMHSO Out
*
Low Horizontal timing output
26 CAMVSO Out
*
Low Vertical timing output
27 CAMCKO Out
CLK
Low Clock output
28 GND
- GND
- Common GROUND
29 VDD
30 AUTO
31 MODE0
32 MODE1
- PWR
- CORE power source
In
High
PD *2 Auto register setting enable signal
In
DATA
PD *2 Auto register setting mode select bit 0
In
DATA
PD *2 Auto register setting mode select bit 1
33 VOUT
Out Analog
-
Analog composite output
34 AVSS
- GND
- Analog GROUND for DAC
35 IREF
Out Analog
- Reference voltage for DAC
36 AVDD
- PWR
- Analog power source for DAC
37 GND
- GND
38 VDDI2C - PWR
39
SDA
In/Out DATA
- Common GROUND
-
Digital IO power source
(For 2-line serial interface input/output)
In 2-line serial interface data input/output
40
SDC
In/Out CLK
In 2-line serial interface clock input
41 RESETB
42 TEST
In
In
Low
High
-
PD *2
System reset signal
Test mode terminal (Connect to GND)
43 GND
- GND
- Common GROUND
44 VDDIO
- PWR
- Digital IO power source
45 WPB
Out Low
Low Write protect signal to EEPROM
46 SCEB
Out Low
High Chip select signal to EEPROM
47 SCK
Out CLK
Low SPI-bus clock
48 SDO
Out DATA
Low SPI-bus data output
※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register.
※ Init column indicates pin status when released from reset.
※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD.
*1 Fig.3 Equivalent Circuit Structures of input / output pins reference
*2 Pull-down status.
Power
Source
System
1
1
1
1,2,4
4
1
1
1
3
3
3
3
1,2,4
2
2
2
1
1
1,2,4
1
1
1
1
1
I/O
type*1
F
F
F
-
-
D
D
D
H
-
I
-
-
-
G
G
B
D
-
-
F
F
F
F
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
5/18
2010.02 - Rev.C
5 Page 
BU6520KV,BU6521KV
4. SPI-bus Interface Timing
SCK
ｔSPCS
ｔSPDV
SCEB
SDO
SDI
ｔSPS
ｔSPH
Fig.8 SPI-bus Interface Timing
Symbol
Description
tSPCLK
dSPCLK
Clock Cycle
Clock Duty
tSPCS
SCK Rise SCEB Setup Time
tSPCH
SCEB Rise after SCK Rise Time
tSPDV
Decision of SDO from SCK Fall
tSPS SCK Rise SDI Setup Time
tSPH SCK Rise SDI Hold Time
*1 Default status right after reset
Technical Note
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ｔSPCH
MIN
2
45
4
2
-
-
-
TYP
736*1
50
738～
1105*1
751*1
-
-
-
MAX
8192
55
12289
8319
28
28
28
Unit
tCAMCKI
%
tCAMCKI
tCAMCKI
ns
ns
ns
When the automatic reading function with the AUTO pin is used, it becomes timing of SCEB to SCK as above.
It is possible to access from the register of BU6520KV/BU6521KV to EEPROM.In that case, SCEB is controlled by the
register.
After the value is set to the register, the SCEB pin is changed into the logic set at once.
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
11/18
2010.02 - Rev.C
11 Page | ||
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