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PDF BU6568GV Data sheet ( Hoja de datos )
| Número de pieza | BU6568GV | |
| Descripción | Camera Image Processors Compatible | |
| Fabricantes | ROHM Semiconductor | |
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For Home Electronics and Security Devices Camera Image Processor Series
Camera Image Processors
Compatible with JPEG Image
BU6566GVW, BU6568GV
No.09061JET02
●Description
BU6566GVW/BU6568GV is a camera image processor compatible with standard JPEG.
Pin-to-Pin compatibility enable support for both standard and high-resolution cameras.
●Features
1)Built-in Camera Module Interface
VGA size (640×480)/BU6566GVW, SXGA size (1280×1024)/BU6568GV for input of image data up to 15 fps (zooming
function is available).
Input data format for YUV=4:2:2, RGB=4:4:4.
Filter processing (image processing) to input images (2 gradations / gray scale / sepia / emboss / edge enhancement/
negative).
Multi-step size reduction down to 1/8 (BU6566GVW), 1/16 (BU6568GV) in X- and Y-direction possible.
Cutting out into an arbitrary size after resizing.
D range enlargement processing of Y (brightness) available in YUV color space to cut images.
Cut images to be stored into an arbitrary position in frame memory in YUV=4:2:2 format.
2-line serial interface built in for camera module control.
2)Built-in frame memory / JPEG code memory
Image frame memory built in (80KB for storing 1 frame of 176x232 @16 bits/pixel).
Display area settable to an arbitrary LCD size.
Data to be stored into image frame memory in YUV=4:2:2 format.
Mask data to be stored into mask frame memory in 1bit/2pixels in YUV=4:2:2 format.
An arbitrary position of frame memory to be updated to camera image according to mask memory.
Image frame memory accessible from HOST CPU (access available both in RGB and YUV).
Rectangular writing function and rectangular reading function for transparent color to image frame memory.
Frame memory usable as JPEG code memory (80KB) to store JPEG compressed images.
Frame memory usable as a ring buffer for JPEG code of 80KB or more.
3)Built-in LCD controller interface
Built-in input/output interface to LCD controller
For display colors of 262144 colors / 65536 colors / 4096 colors.
Up to 2 LCD module controllers controllable.
Arbitrary rectangular selection in frame memory to be transferred to LCD controller.
4)Built-in JPEG CODEC
ISO/IEC10918 conforming base line method.
･Compression
For YUV=4:2:2 only.
Quantization table selectable from 20 built-in tables.
･Decompression
For YUV=4:4:4, 4:2:2(horizontal sub-sampling:BU6566GVW),
4:2:0, 4:1:1(horizontal sub-sampling:BU6566GVW), and gray scale.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/16
2009.04 - Rev.B
1 page  
BU6566GVW, BU6568GV
●Terminal functions
PIN Land
No. No.
PIN Name
In
/Out
1 A1 N.C.
-
2 B2 VDDIO1
-
D15/HOST_MODE In/Out
3 B1
D15/EXGIO7
In/Out
4
C2 D14/EXGIO6
In/Out
5 C1 N.C.
-
6
D3 D13/EXGIO5
In/Out
7
D2 D12/EXGIO4
In/Out
8 D1 D11/EXGIO3 In/Out
9
E1 D10/EXGIO2
In/Out
10 E2 D9/EXGIO1
In/Out
11 E3 D8/EXGIO0
In/Out
12 E4 GND
-
13 F5 VDD
-
14 F4 D7
In/Out
15 F3 D6
In/Out
16 F2 D5
In/Out
17 F1 D4
In/Out
18 G1 D3
In/Out
19 G2 D2
In/Out
D1/SIF_RD
20 G3
D1
In/Out
In/Out
D0/SIF/WD
21 H1
D0
22 H2 N.C.
23 J1 A2
24 G4 GND
25 H3 N.C.
26 K1 N.C.
27 J2 VDDIO1
In/Out
In/Out
-
In
-
-
-
-
A1/SIF_CD
28 K2
A1
In
In
CSB/SIF_CS1
29 J3
CSB
In
In
WRB/SIF_SCK
In
30 K3
WRB
31 H4 RDB
32 J4 N.C.
33 K4 INT
34 K5 CAMVS
35 J5 CAMHS
36 H5 CAMD0
37 G5 CAMD1
38 F6 CAMD2
39 G6 CAMD3
40
H6
GIO2
/ KEY2
In
In
-
Out
In
In
In
In
In
In
In/Out
41 J6 CAMD4
42 K6 CAMD5
43 K7 CAMD6
44 J7 CAMD7
45 H7 VDDIO2
46 K8 CAMCKI
47 J8 N.C.
In
In
In
In
-
In
-
48 K9 CAMCKO
Out
Active
Level
-
PWR
DATA
DATA
DATA
-
DATA
DATA
DATA
DATA
DATA
DATA
GND
PWR
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
-
DATA
GND
-
-
PWR
DATA
DATA
Low
Low
Low
Low
Low
-
＊
＊
＊
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
PWR
CLK
-
CLK
Technical Note
www.DataSheet4U.com
Init
-
-
IN *1
IN *1
IN *1
-
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
-
-
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
IN *1
-
- *2
-
-
-
-
-
-
-*2
-
Low
-
-
-
-
-
-
Out/Lo
w
-
-
-
-
-
-
-
Low
Function explanation
Function
division
-
Digital I/O power source (system 1)
Switch parallel / Serial of HOST I/F (BU6566GVW
Host data bus bit 15
Host data bus bit 14
-
Host data bus bit 13
Host data bus bit 12
Host data bus bit 11
Host data bus bit 10
Host data bus bit 9
Host data bus bit 8
Common ground
Digital core power source
Host data bus bit 7
Host data bus bit 6
Host data bus bit 5
Host data bus bit 4
Host data bus bit 3
Host data bus bit 2
Host data bus bit 1
Serial data from BU6566GVW to HOST
Host data bus bit 1
Host data bus bit 0
Serial data from HOST to BU6566GVW
Host data bus bit 0
-
Host data bus bit 2
Common ground
-
-
Digital I/O power source (system 1)
Host address bus bit 1 signal
Command / data identification in HOST serial I/F(BU6566GVW
Host address bus bit 1
Chip select signal
Chip select signal in HOST serial I/F(BU6566GVW only)
Chip select signal
Write enable signal
Serial clock in HOST serial I/F(BU6566GVW only)
Write enable signal
Read enable signal
-
Interruption signal
Camera vertical timing signal (pull down at CAMOFF)
Camera horizontal timing signal (pull down at CAMOFF)
Camera data input bit0 (pull down at CAMOFF)
Camera data input bit1 (pull down at CAMOFF)
Camera data input bit2 (pull down at CAMOFF)
Camera data input bit3 (pull down at CAMOFF)
General purpose I/O2
/ Key input2 (pull down for register control)
Camera data input bit4 (pull down at CAMOFF)
Camera data input bit5 (pull down at CAMOFF)
Camera data input bit6 (pull down at CAMOFF)
Camera data input bit7 (pull down at CAMOFF)
Digital I/O power source (system 2)
Camera clock input (pull down at CAMOFF)
-
Camera clock output
-
-
HOST IF
HOST IF
-
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
-
-
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
HOST IF
-
HOST IF
-
-
-
HOST IF
HOST IF
HOST IF
HOST IF
-
HOST IF
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
SYSTEM
CAMERA
CAMERA
CAMERA
CAMERA
-
CAMERA
-
CAMERA
I/O type
BU6566GV
W
-
-
F*3
-
F
-
F
F
F
F
F
F
-
-
E
E
E
E
E
E
E
-
E
-
-
A
-
-
-
A
-
A
-
C
-
C
-
D
B
B
B
B
B
B
H
B
B
B
B
-
B
-
D
I/O
type
BU6568G
V
-
-
-
H
H
-
H
H
H
H
H
H
-
-
G
G
G
G
G
G
-
G
-
G
-
A
-
-
-
-
A
-
K
-
K
K
-
D
B
B
B
B
B
B
H
B
B
B
B
-
B
-
D
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/16
2009.04 - Rev.B
5 Page 
BU6566GVW, BU6568GV
2. Camera Module Interface Timing
2.1. System clock and camera clock
Technical Note
www.DataSheet4U.com
External input clock (XIN) may be divided set and supplied as CAMCKO clock to camera module.
The relation of data synchronization clock CAMCKI clock from camera and system clock SCLK must be set so as to meet the
following formula.
fSCLK 2 × fCAMCKI
……(2.1-1)
fSCLK
System clock frequency
fCAMCKI
Camera clock frequency input to CAMCKI terminal
Moreover, [Camera timing 1] or [Camera timing 2] shown below must be satisfied.
[Camera timing１] (In the case when CAMCKI signal is as asynchronous as CAMCKO)
tCAMCKIH > tSCLK + 1ns and tCAMCKIL > tSCLK + 1ns ……(2.1-2)
tCAMCKIH
CAMCKI High interval
tCAMCKIL
CAMCKI Low interval
[Camera timing 2] (In the case when CAMCKI signal is as synchronous as CAMCKO)
total delay + margin ( 10ns) < tSCLK
……(2.1-3)
total delay
delay from CAMCKO change point to CAMCKI change point
The clock relation in fSCLK = fCAMCKO = 2 × fCAMCKI is shown in Figure.2.1-1.
[fSCLK=fCAMCKO=2 × fCAMCKI]
internal SCLK
CAMCKO
CAMCKI
total delay
detect
CAMCKI = "H"
CAMCKO
detect
CAMCKI = "L"
BU6566GVW total
delay
/BU6568GV
CAMCKI
CAMERA
Module
Figure .2.1-1 Relation between system clock and camera clock
2.2. Camera module interface timing
The timing of the camera image signal in camera I/F is shown in Table 2.2-1.
CAMVS
CAMHS
CAMD0
－CAMD7
CAMCKI
(CKPL=“0”)
CAMCKI
(CKPOL=“1”)
tCMS
tCMH
Table 2.2-1 BU6566GVW/BU6568GV timing (camera data)
Symbol
Details
MIN. TYP. MAX. Unit
tCMS CAMCKI rising/falling camera set up time
1/5 -
-
ns
tCMH CAMCKI rising/falling camera hold time
1/5 -
-
ns
Remarks
BU6566GVW/BU6568GV
BU6566GVW/BU6568GV
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/16
2009.04 - Rev.B
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet BU6568GV.PDF ] | |
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